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soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage 

This patch overrides EnableTcoTimer FSP UPD default value based on
PmTimerDisabled coreboot devcietree config.

BRANCH=none
BUG=b:138152075

Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Subrata Banik 2019-07-29 14:21:55 +05:30
parent ed9ea86ba3
commit 06cc764483
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/cannonlake/fsp_params.c
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@ -367,6 +367,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
/* Disable PCH ACPI timer */
params->EnableTcoTimer = !config->PmTimerDisabled;
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;