mb/google/sarien: Fix SSD's power off sequence before going to S5
BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -40,8 +40,9 @@ Method (MPTS, 1)
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/* Clear SSD EN adn RST pin to avoid leakage */
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If (Arg0 == 5) {
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\_SB.PCI0.CTXS (SSD_EN)
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\_SB.PCI0.CTXS (SSD_RST)
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Sleep(1)
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\_SB.PCI0.CTXS (SSD_EN)
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}
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}
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@ -40,8 +40,9 @@ Method (MPTS, 1)
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/* Clear SSD EN adn RST pin to avoid leakage */
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If (Arg0 == 5) {
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\_SB.PCI0.CTXS (SSD_EN)
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\_SB.PCI0.CTXS (SSD_RST)
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Sleep(1)
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\_SB.PCI0.CTXS (SSD_EN)
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}
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}
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