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mb/google/sarien: Fix SSD's power off sequence before going to S5 

BUG=b:133389422
TEST=check SSD's power off sequence to meet PCIE requirement.
     SSD's reset should be cleared before clearing SSD's power EN Pin.

Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Roy Mingi Park 2019-06-03 16:11:25 -07:00 committed by Duncan Laurie
parent 13539d2f9d
commit 06cfb21e24
2 changed files with 4 additions and 2 deletions
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3
src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
View File

@ -40,8 +40,9 @@ Method (MPTS, 1)
/* Clear SSD EN adn RST pin to avoid leakage */ /* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) { If (Arg0 == 5) {
\_SB.PCI0.CTXS (SSD_EN)
\_SB.PCI0.CTXS (SSD_RST) \_SB.PCI0.CTXS (SSD_RST)
Sleep(1)
\_SB.PCI0.CTXS (SSD_EN)
} }
} }

3
src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
View File

@ -40,8 +40,9 @@ Method (MPTS, 1)
/* Clear SSD EN adn RST pin to avoid leakage */ /* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) { If (Arg0 == 5) {
\_SB.PCI0.CTXS (SSD_EN)
\_SB.PCI0.CTXS (SSD_RST) \_SB.PCI0.CTXS (SSD_RST)
Sleep(1)
\_SB.PCI0.CTXS (SSD_EN)
} }
} }