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mb/intel/galileo: Drop the FSP1.1 option 

This board is EOL and has FSP2.0 support, so drop the older
version.

Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2019-01-16 02:57:30 +01:00 committed by Patrick Georgi
parent b1c57d1beb
commit 06e33226b3
13 changed files with 12 additions and 679 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
configs/config.intel_galileo_gen2.fsp1.1
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@ -1,9 +0,0 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
CONFIG_FSP_VERSION_1_1=y
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_921600=y

59
src/mainboard/intel/galileo/Kconfig
View File

@ -23,6 +23,10 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_QUARK
select MAINBOARD_HAS_I2C_TPM_ATMEL
select MAINBOARD_HAS_TPM2
select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING
select POSTCAR_STAGE
config MAINBOARD_DIR
string
@ -45,31 +49,6 @@ config GALILEO_GEN2
runtime. Select which generation of the Galileo that coreboot
should initialize.
choice
prompt "FSP version"
default FSP_VERSION_2_0
config FSP_VERSION_1_1
bool "FSP 1.1"
select PLATFORM_USES_FSP1_1
# select ADD_FSP_RAW_BIN
help
Use FSP 1_1 binary
config FSP_VERSION_2_0
bool "FSP 2.0"
select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING
select POSTCAR_STAGE
help
Use FSP 2.0 binary
endchoice
config FSP_VERSION
string
default "fsp1_1" if FSP_VERSION_1_1
default "fsp2_0" if FSP_VERSION_2_0
choice
prompt "FSP binary type"
default FSP_BUILD_TYPE_DEBUG
@ -92,28 +71,14 @@ config FSP_BUILD_TYPE
choice
prompt "FSP type"
depends on FSP_VERSION_2_0 || FSP_VERSION_1_1
default FSP_TYPE_1_1_PEI if FSP_VERSION_1_1
default FSP_TYPE_2_0_PEI if FSP_VERSION_2_0
default FSP_TYPE_2_0_PEI
config FSP_TYPE_1_1
bool "MemInit subroutine"
depends on FSP_VERSION_1_1
help
FSP 1.1 implemented as subroutines, no EDK-II cores
config FSP_TYPE_1_1_PEI
bool "SEC + PEI Core + MemInit PEIM"
depends on FSP_VERSION_1_1
help
FSP 1.1 implemented using SEC and PEI core
config FSP_TYPE_2_0
bool "MemInit subroutine"
depends on FSP_VERSION_2_0
help
FSP 2.0 implemented as subroutines, no EDK-II cores
config FSP_TYPE_2_0_PEI
bool "SEC + PEI Core + MemInit PEIM"
depends on FSP_VERSION_2_0
help
FSP 2.0 implemented using SEC and PEI core
@ -121,26 +86,22 @@ endchoice
config FSP_TYPE
string
default "Fsp1_1" if FSP_TYPE_1_1
default "Fsp1_1Pei" if FSP_TYPE_1_1_PEI
default "Fsp2_0" if FSP_TYPE_2_0
default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI
config FSP_DEBUG_ALL
bool "Enable all FSP debug support"
depends on FSP_VERSION_2_0 || FSP_VERSION_1_1
default y
# Enable display and verification for coreboot build tests
select DISPLAY_HOBS
select DISPLAY_MTRRS
select DISPLAY_SMM_MEMORY_MAP
select DISPLAY_UPD_DATA
select DISPLAY_ESRAM_LAYOUT if FSP_VERSION_2_0
select DISPLAY_FSP_CALLS_AND_STATUS if FSP_VERSION_2_0
select DISPLAY_FSP_HEADER if FSP_VERSION_2_0
select POSTCAR_CONSOLE if FSP_VERSION_2_0
select VERIFY_HOBS if FSP_VERSION_2_0
select DISPLAY_FSP_ENTRY_POINTS if FSP_VERSION_1_1
select DISPLAY_ESRAM_LAYOUT
select DISPLAY_FSP_CALLS_AND_STATUS
select DISPLAY_FSP_HEADER
select POSTCAR_CONSOLE
select VERIFY_HOBS
help
Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,

4
src/mainboard/intel/galileo/Makefile.inc
View File

@ -13,9 +13,7 @@
## GNU General Public License for more details.
##
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0)$(CONFIG_PLATFORM_USES_FSP1_1),y)
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/$(CONFIG_FSP_VERSION)/quark
endif
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/quark
bootblock-y += gpio.c
bootblock-y += reg_access.c

27
src/mainboard/intel/galileo/romstage.c
View File

@ -1,26 +1 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/romstage.h>
/* All FSP specific code goes in this block */
void mainboard_romstage_entry(struct romstage_params *rp)
{
/* Call back into chipset code with platform values updated. */
romstage_common(rp);
}
#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */
/* Dummy */

49
src/soc/intel/quark/Kconfig
View File

@ -107,17 +107,6 @@ config ENABLE_DEBUG_LED_ESRAM
Indicate that ESRAM has been successfully initialized. If the SD LED
does not light then the ESRAM initialization needs to be debugged.
config ENABLE_DEBUG_LED_FINDFSP
bool "SD LED indicates fsp.bin file was found"
depends on PLATFORM_USES_FSP1_1
default n
select ENABLE_DEBUG_LED
help
Indicate that fsp.bin was found. If the SD LED does not light then
the code between ESRAM initialization through find_fsp needs to
debugged. Start by verifying that the correct fsp.bin is in the
image.
config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
bool "SD LED indicates bootblock.c successfully entered"
default n
@ -160,12 +149,10 @@ config ENABLE_DEBUG_LED_SOC_INIT_ENTRY
config DCACHE_RAM_BASE
hex
default 0x80070000 if PLATFORM_USES_FSP1_1
default 0x80000000
config DCACHE_RAM_SIZE
hex
default 0x8000 if PLATFORM_USES_FSP1_1
default 0x40000
config DISPLAY_ESRAM_LAYOUT
@ -197,48 +184,12 @@ config CBFS_SIZE
# SoC code to boot coreboot and its payload.
#####
config ADD_FSP_RAW_BIN
bool "Add the Intel FSP binary to the flash image without relocation"
default n
depends on PLATFORM_USES_FSP1_1
help
Select this option to add an Intel FSP binary to
the resulting coreboot image.
Note: Without this binary, coreboot builds relying on the FSP
will not boot
config FSP_FILE
string "Intel FSP binary path and filename"
default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP.fd"
depends on PLATFORM_USES_FSP1_1
depends on ADD_FSP_RAW_BIN
help
The path and filename of the Intel FSP binary for this platform.
config FSP_LOC
hex
default 0xfff80000
depends on PLATFORM_USES_FSP1_1
help
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
config FSP_ESRAM_LOC
hex
default 0x80000000 if PLATFORM_USES_FSP1_1
default 0x80040000
help
The location in ESRAM where a copy of the FSP binary is placed.
config RELOCATE_FSP_INTO_DRAM
bool "Relocate FSP into DRAM"
default n
depends on PLATFORM_USES_FSP1_1
help
Relocate the FSP binary into DRAM before the call to SiliconInit.
config FSP_M_FILE
string
depends on PLATFORM_USES_FSP2_0

1
src/soc/intel/quark/Makefile.inc
View File

@ -49,7 +49,6 @@ postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += chip.c
ramstage-y += ehci.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
ramstage-y += gpio_i2c.c
ramstage-y += i2c.c

35
src/soc/intel/quark/fsp1_1.c
View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <fsp/util.h>
#include <soc/ramstage.h>
void fsp_silicon_init(bool s3wake)
{
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
intel_silicon_init();
else
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake);
}
void soc_silicon_init_params(SILICON_INIT_UPD *upd)
{
}
void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
SILICON_INIT_UPD *new)
{
}

4
src/soc/intel/quark/include/soc/pm.h
View File

@ -25,10 +25,6 @@ struct chipset_power_state {
} __packed;
struct chipset_power_state *get_power_state(void);
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
struct chipset_power_state *fill_power_state(void);
#else
int fill_power_state(void);
#endif
#endif /* _SOC_PM_H_ */

6
src/soc/intel/quark/include/soc/ramstage.h
View File

@ -20,15 +20,9 @@
#include <arch/cpu.h>
#include <chip.h>
#include <device/device.h>
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/ramstage.h>
#endif
#include <soc/QuarkNcSocId.h>
void mainboard_gpio_i2c_init(struct device *dev);
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
void fsp_silicon_init(bool s3wake);
#endif
asmlinkage void chipset_teardown_car(void);
#endif /* _SOC_RAMSTAGE_H_ */

4
src/soc/intel/quark/include/soc/romstage.h
View File

@ -22,11 +22,7 @@
#error "Don't include romstage.h from a ramstage compilation unit!"
#endif
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/romstage.h>
#else
#include <soc/car.h>
#endif
#include <soc/reg_access.h>
asmlinkage void *car_stage_c_entry(void);

1
src/soc/intel/quark/romstage/Makefile.inc
View File

@ -19,7 +19,6 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
endif # CONFIG_PLATFORM_USES_FSP2_0
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
romstage-y += mtrr.c
romstage-y += pcie.c
romstage-y += report_platform.c

247
src/soc/intel/quark/romstage/fsp1_1.c
View File

@ -1,247 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/early_variables.h>
#include <console/console.h>
#include "../chip.h"
#include <fsp/memmap.h>
#include <fsp/util.h>
#include <soc/pci_devs.h>
#include <soc/QuarkNcSocId.h>
#include <soc/romstage.h>
#include <string.h>
extern void asmlinkage light_sd_led(void);
asmlinkage void *car_stage_c_entry(void)
{
FSP_INFO_HEADER *fih;
struct cache_as_ram_params car_params = {0};
void *top_of_stack;
post_code(0x20);
/* Copy the FSP binary into ESRAM */
memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC,
0x00040000);
/* Locate the FSP header in ESRAM */
fih = find_fsp(CONFIG_FSP_ESRAM_LOC);
if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP))
light_sd_led();
/* Start the early verstage/romstage code */
post_code(0x2A);
car_params.fih = fih;
top_of_stack = cache_as_ram_main(&car_params);
/* Initialize MTRRs and switch stacks after RAM initialized */
return top_of_stack;
}
static struct chipset_power_state power_state CAR_GLOBAL;
struct chipset_power_state *get_power_state(void)
{
return (struct chipset_power_state *)car_get_var_ptr(&power_state);
}
struct chipset_power_state *fill_power_state(void)
{
struct chipset_power_state *ps = get_power_state();
ps->prev_sleep_state = 0;
printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state);
return ps;
}
size_t mmap_region_granularity(void)
{
/* Align to 8 MiB by default */
return 8 << 20;
}
/* Initialize the UPD parameters for MemoryInit */
void soc_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *upd)
{
const struct device *dev;
const struct soc_intel_quark_config *config;
void *rmu_data;
size_t rmu_data_len;
/* Locate the configuration data from devicetree.cb */
dev = pcidev_path_on_root(LPC_DEV_FUNC);
if (!dev) {
printk(BIOS_CRIT,
"Error! Device (PCI:0:%02x.%01x) not found, "
"soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC,
PCI_FUNCTION_NUMBER_QNC_LPC);
return;
}
config = dev->chip_info;
/* Clear SMI and wake events */
clear_smi_and_wake_events();
/* Locate the RMU data file in flash */
rmu_data = locate_rmu_file(&rmu_data_len);
if (!rmu_data)
die("Microcode file (rmu.bin) not found.");
/* Display the ESRAM layout */
if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) {
printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
printk(BIOS_SPEW,
"+-------------------+ 0x80080000 - ESRAM end\n");
if (_car_relocatable_data_end != (void *)0x80080000) {
printk(BIOS_SPEW, "| |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
_car_relocatable_data_end);
}
printk(BIOS_SPEW, "| coreboot data |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
_car_stack_end);
printk(BIOS_SPEW, "| coreboot stack |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%p",
_car_stack_start);
if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) {
printk(BIOS_SPEW, "\n");
printk(BIOS_SPEW, "| vboot data |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%08x",
CONFIG_DCACHE_RAM_BASE);
}
printk(BIOS_SPEW, " (CONFIG_DCACHE_RAM_BASE)\n");
printk(BIOS_SPEW, "| FSP data |\n");
printk(BIOS_SPEW, "+-------------------+\n");
printk(BIOS_SPEW, "| FSP stack |\n");
printk(BIOS_SPEW, "+-------------------+\n");
printk(BIOS_SPEW, "| FSP binary |\n");
printk(BIOS_SPEW,
"+-------------------+ 0x80000000 - ESRAM start\n\n");
}
/* Update the UPD data for MemoryInit */
upd->AddrMode = config->AddrMode;
upd->ChanMask = config->ChanMask;
upd->ChanWidth = config->ChanWidth;
upd->DramDensity = config->DramDensity;
upd->DramRonVal = config->DramRonVal;
upd->DramRttNomVal = config->DramRttNomVal;
upd->DramRttWrVal = config->DramRttWrVal;
upd->DramSpeed = config->DramSpeed;
upd->DramType = config->DramType;
upd->DramWidth = config->DramWidth;
upd->EccScrubBlkSize = config->EccScrubBlkSize;
upd->EccScrubInterval = config->EccScrubInterval;
upd->Flags = config->Flags;
upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
upd->RankMask = config->RankMask;
upd->RmuBaseAddress = (uintptr_t)rmu_data;
upd->RmuLength = rmu_data_len;
upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
? (uintptr_t)fsp_write_line : 0;
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
config->SmmTsegSize : 0;
upd->SocRdOdtVal = config->SocRdOdtVal;
upd->SocWrRonVal = config->SocWrRonVal;
upd->SocWrSlewRate = config->SocWrSlewRate;
upd->SrInt = config->SrInt;
upd->SrTemp = config->SrTemp;
upd->tCL = config->tCL;
upd->tFAW = config->tFAW;
upd->tRAS = config->tRAS;
upd->tRRD = config->tRRD;
upd->tWTR = config->tWTR;
}
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
MEMORY_INIT_UPD *new)
{
/* Display the parameters for MemoryInit */
printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
fsp_display_upd_value("AddrMode", sizeof(old->AddrMode),
old->AddrMode, new->AddrMode);
fsp_display_upd_value("ChanMask", sizeof(old->ChanMask),
old->ChanMask, new->ChanMask);
fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth),
old->ChanWidth, new->ChanWidth);
fsp_display_upd_value("DramDensity", sizeof(old->DramDensity),
old->DramDensity, new->DramDensity);
fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal),
old->DramRonVal, new->DramRonVal);
fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal),
old->DramRttNomVal, new->DramRttNomVal);
fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal),
old->DramRttWrVal, new->DramRttWrVal);
fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed),
old->DramSpeed, new->DramSpeed);
fsp_display_upd_value("DramType", sizeof(old->DramType),
old->DramType, new->DramType);
fsp_display_upd_value("DramWidth", sizeof(old->DramWidth),
old->DramWidth, new->DramWidth);
fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize),
old->EccScrubBlkSize, new->EccScrubBlkSize);
fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval),
old->EccScrubInterval, new->EccScrubInterval);
fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags,
new->Flags);
fsp_display_upd_value("FspReservedMemoryLength",
sizeof(old->FspReservedMemoryLength),
old->FspReservedMemoryLength, new->FspReservedMemoryLength);
fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask,
new->RankMask);
fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress),
old->RmuBaseAddress, new->RmuBaseAddress);
fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
old->RmuLength, new->RmuLength);
fsp_display_upd_value("SerialPortPollForChar",
sizeof(old->SerialPortPollForChar),
old->SerialPortPollForChar, new->SerialPortPollForChar);
fsp_display_upd_value("SerialPortReadChar",
sizeof(old->SerialPortReadChar),
old->SerialPortReadChar, new->SerialPortReadChar);
fsp_display_upd_value("SerialPortWriteChar",
sizeof(old->SerialPortWriteChar),
old->SerialPortWriteChar, new->SerialPortWriteChar);
fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
old->SmmTsegSize, new->SmmTsegSize);
fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
old->SocRdOdtVal, new->SocRdOdtVal);
fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal),
old->SocWrRonVal, new->SocWrRonVal);
fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate),
old->SocWrSlewRate, new->SocWrSlewRate);
fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt,
new->SrInt);
fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp,
new->SrTemp);
fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL);
fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW);
fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS);
fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD);
fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR);
}
void soc_after_ram_init(struct romstage_params *params)
{
/* Disable the ROM shadow 0x000e0000 - 0x000fffff */
disable_rom_shadow();
/* Initialize the PCIe bridges */
pcie_init();
}

245
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
View File

@ -1,245 +0,0 @@
/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPDVPD_H__
#define __FSPUPDVPD_H__
#pragma pack(1)
#define MAX_CHANNELS_NUM 1
#define MAX_DIMMS_NUM 1
typedef struct {
UINT8 DimmId;
UINT32 SizeInMb;
UINT16 MfgId;
/** Module part number for DDR3 is 18 bytes however for
DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
**/
UINT8 ModulePartNum[20];
} DIMM_INFO;
typedef struct {
UINT8 ChannelId;
UINT8 DimmCount;
DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
} CHANNEL_INFO;
typedef struct {
UINT8 Revision;
UINT16 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
UINT8 MemoryType;
UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
UINT8 ChannelCount;
CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
} FSP_SMBIOS_MEMORY_INFO;
typedef struct {
/** Offset 0x0018
**/
UINT64 Signature;
/** Offset 0x0020
**/
UINT64 Revision;
/** Offset 0x0028
**/
UINT32 RmuBaseAddress;
/** Offset 0x002C
**/
UINT32 RmuLength;
/** Offset 0x0030
**/
UINT32 Reserved_30;
/** Offset 0x0034
**/
UINT32 tRAS;
/** Offset 0x0038
**/
UINT32 tWTR;
/** Offset 0x003C
**/
UINT32 tRRD;
/** Offset 0x0040
**/
UINT32 tFAW;
/** Offset 0x0044
**/
UINT32 Flags;
/** Offset 0x0048
**/
UINT8 DramWidth;
/** Offset 0x0049
**/
UINT8 DramSpeed;
/** Offset 0x004A
**/
UINT8 DramType;
/** Offset 0x004B
**/
UINT8 RankMask;
/** Offset 0x004C
**/
UINT8 ChanMask;
/** Offset 0x004D
**/
UINT8 ChanWidth;
/** Offset 0x004E
**/
UINT8 AddrMode;
/** Offset 0x004F
**/
UINT8 SrInt;
/** Offset 0x0050
**/
UINT8 SrTemp;
/** Offset 0x0051
**/
UINT8 DramRonVal;
/** Offset 0x0052
**/
UINT8 DramRttNomVal;
/** Offset 0x0053
**/
UINT8 DramRttWrVal;
/** Offset 0x0054
**/
UINT8 SocRdOdtVal;
/** Offset 0x0055
**/
UINT8 SocWrRonVal;
/** Offset 0x0056
**/
UINT8 SocWrSlewRate;
/** Offset 0x0057
**/
UINT8 DramDensity;
/** Offset 0x0058
**/
UINT8 tCL;
/** Offset 0x0059
**/
UINT8 EccScrubInterval;
/** Offset 0x005A
**/
UINT8 EccScrubBlkSize;
/** Offset 0x005B
**/
UINT8 SmmTsegSize;
/** Offset 0x005C
**/
UINT32 FspReservedMemoryLength;
/** Offset 0x0060
**/
UINT32 MrcDataPtr;
/** Offset 0x0064
**/
UINT32 MrcDataLength;
/** Offset 0x0068
**/
UINT32 SerialPortPollForChar;
/** Offset 0x006C
**/
UINT32 SerialPortReadChar;
/** Offset 0x0070
**/
UINT32 SerialPortWriteChar;
/** Offset 0x0074
**/
UINT8 ReservedMemoryInitUpd[12];
} MEMORY_INIT_UPD;
typedef struct {
/** Offset 0x0080
**/
UINT64 Signature;
/** Offset 0x0088
**/
UINT64 Revision;
/** Offset 0x0090
**/
UINT16 PcdRegionTerminator;
} SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
typedef struct _UPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 Signature;
/** Offset 0x0008
**/
UINT64 Revision;
/** Offset 0x0010
**/
UINT32 MemoryInitUpdOffset;
/** Offset 0x0014
**/
UINT32 SiliconInitUpdOffset;
/** Offset 0x0018
**/
MEMORY_INIT_UPD MemoryInitUpd;
/** Offset 0x0080
**/
SILICON_INIT_UPD SiliconInitUpd;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */
#define FSP_IMAGE_REV 0x00000000
typedef struct _VPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 PcdVpdRegionSign;
/** Offset 0x0008
PcdImageRevision
**/
UINT32 PcdImageRevision;
/** Offset 0x000C
**/
UINT32 PcdUpdRegionOffset;
} VPD_DATA_REGION;
#pragma pack()
#endif