soc/intel/baytrail/acpi.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -125,18 +125,18 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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return current;
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}
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static acpi_tstate_t baytrail_tss_table[] = {
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static acpi_tstate_t soc_tss_table[] = {
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{ 100, 1000, 0, 0x00, 0 },
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{ 88, 875, 0, 0x1e, 0 },
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{ 75, 750, 0, 0x1c, 0 },
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{ 63, 625, 0, 0x1a, 0 },
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{ 50, 500, 0, 0x18, 0 },
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{ 38, 375, 0, 0x16, 0 },
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{ 25, 250, 0, 0x14, 0 },
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{ 13, 125, 0, 0x12, 0 },
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{ 88, 875, 0, 0x1e, 0 },
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{ 75, 750, 0, 0x1c, 0 },
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{ 63, 625, 0, 0x1a, 0 },
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{ 50, 500, 0, 0x18, 0 },
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{ 38, 375, 0, 0x16, 0 },
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{ 25, 250, 0, 0x14, 0 },
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{ 13, 125, 0, 0x12, 0 },
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};
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static void generate_T_state_entries(int core, int cores_per_package)
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static void generate_t_state_entries(int core, int cores_per_package)
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{
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/* Indicate SW_ALL coordination for T-states */
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acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
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@ -148,24 +148,23 @@ static void generate_T_state_entries(int core, int cores_per_package)
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acpigen_write_TPC("\\TLVL");
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/* Write TSS table for MSR access */
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acpigen_write_TSS_package(
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ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table);
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acpigen_write_TSS_package(ARRAY_SIZE(soc_tss_table), soc_tss_table);
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}
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static int calculate_power(int tdp, int p1_ratio, int ratio)
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{
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u32 m;
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u32 power;
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u32 m, power;
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/*
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* M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
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*
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* Power = (ratio / p1_ratio) * m * tdp
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*/
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m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
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m = (m * m) / 1000;
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/*
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* Power = (ratio / p1_ratio) * m * TDP
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*/
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power = ((ratio * 100000 / p1_ratio) / 100);
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power *= (m / 100) * (tdp / 1000);
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power /= 1000;
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@ -173,7 +172,7 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
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return (int)power;
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}
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static void generate_P_state_entries(int core, int cores_per_package)
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static void generate_p_state_entries(int core, int cores_per_package)
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{
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int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
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int coord_type, power_max, power_unit, num_entries;
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@ -232,12 +231,12 @@ static void generate_P_state_entries(int core, int cores_per_package)
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/* Add entry for Turbo ratio */
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acpigen_write_PSS_package(
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clock_max + 1, /*MHz*/
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power_max, /*mW*/
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10, /*lat1*/
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10, /*lat2*/
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control_status, /*control*/
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control_status); /*status*/
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clock_max + 1, /* MHz */
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power_max, /* mW */
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10, /* lat1 */
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10, /* lat2 */
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control_status, /* control */
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control_status); /* status */
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} else {
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/* _PSS package count without Turbo */
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acpigen_write_package(num_entries + 1);
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@ -248,12 +247,12 @@ static void generate_P_state_entries(int core, int cores_per_package)
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/* First regular entry is max non-turbo ratio */
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control_status = (ratio_max << 8) | vid_max;
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acpigen_write_PSS_package(
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clock_max, /*MHz*/
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power_max, /*mW*/
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10, /*lat1*/
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10, /*lat2*/
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control_status, /*control */
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control_status); /*status*/
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clock_max, /* MHz */
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power_max, /* mW */
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10, /* lat1 */
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10, /* lat2 */
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control_status, /* control */
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control_status); /* status */
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/* Set up ratio and vid ranges for VID calculation */
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ratio_range_2 = (ratio_turbo - ratio_min) * 2;
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@ -264,8 +263,8 @@ static void generate_P_state_entries(int core, int cores_per_package)
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ratio >= ratio_min; ratio -= ratio_step) {
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/* Calculate VID for this ratio */
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vid = ((ratio - ratio_min) * vid_range_2) /
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ratio_range_2 + vid_min;
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vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min;
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/* Round up if remainder */
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if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
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vid++;
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@ -276,12 +275,12 @@ static void generate_P_state_entries(int core, int cores_per_package)
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control_status = (ratio << 8) | (vid & 0xff);
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acpigen_write_PSS_package(
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clock, /*MHz*/
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power, /*mW*/
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10, /*lat1*/
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10, /*lat2*/
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control_status, /*control*/
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control_status); /*status*/
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clock, /* MHz */
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power, /* mW */
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10, /* lat1 */
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10, /* lat2 */
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control_status, /* control */
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control_status); /* status */
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}
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/* Fix package length */
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@ -301,20 +300,16 @@ void generate_cpu_entries(const struct device *device)
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}
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/* Generate processor \_SB.CPUx */
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acpigen_write_processor(
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core, pcontrol_blk, plen);
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acpigen_write_processor(core, pcontrol_blk, plen);
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/* Generate P-state tables */
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generate_P_state_entries(
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core, pattrs->num_cpus);
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generate_p_state_entries(core, pattrs->num_cpus);
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/* Generate C-state tables */
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acpigen_write_CST_package(
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cstate_map, ARRAY_SIZE(cstate_map));
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acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map));
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/* Generate T-state tables */
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generate_T_state_entries(
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core, pattrs->num_cpus);
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generate_t_state_entries(core, pattrs->num_cpus);
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acpigen_pop_len();
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}
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@ -343,8 +338,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
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sci_flags |= MP_IRQ_POLARITY_HIGH;
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irqovr = (void *)current;
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current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
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sci_flags);
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current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags);
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return current;
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}
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