cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" the SMRR MSR are at a different offset for model_6fx and model_1067x. This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL. Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -37,6 +37,10 @@
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#define G_SMRAME (1 << 3)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define IA32_FEATURE_CONTROL 0x3a
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#define FEATURE_CONTROL_LOCK_BIT (1 << 0)
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#define SMRR_ENABLE (1 << 3)
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struct ied_header {
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struct ied_header {
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char signature[10];
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char signature[10];
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u32 size;
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u32 size;
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@ -57,12 +61,32 @@ struct smm_relocation_params {
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static struct smm_relocation_params smm_reloc_params;
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static struct smm_relocation_params smm_reloc_params;
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static void *default_smm_area = NULL;
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static void *default_smm_area = NULL;
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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static void write_smrr(struct smm_relocation_params *relo_params)
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{
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{
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struct cpuinfo_x86 c;
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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/* Both model_6fx and model_1067x SMRR function slightly differently
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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from the rest. The MSR are at different location from the rest
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and need to be explicitly enabled. */
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get_fms(&c, cpuid_eax(1));
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if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) {
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msr_t msr;
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msr = rdmsr(IA32_FEATURE_CONTROL);
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/* SMRR enabled and feature locked */
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if (!((msr.lo & SMRR_ENABLE)
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&& (msr.lo & FEATURE_CONTROL_LOCK_BIT))) {
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printk(BIOS_WARNING,
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"SMRR not enabled, skip writing SMRR...\n");
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return;
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}
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wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
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} else {
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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}
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}
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/* The relocation work is actually performed in SMM context, but the code
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/* The relocation work is actually performed in SMM context, but the code
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@ -137,7 +161,15 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
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struct cpuinfo_x86 c;
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/* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
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get_fms(&c, cpuid_eax(1));
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if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
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params->smrr_base.lo = (params->smram_base & rmask);
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else
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params->smrr_base.lo = (params->smram_base & rmask)
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| MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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| MTRR_PHYS_MASK_VALID;
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@ -31,6 +31,10 @@
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#define IA32_SMRR_PHYS_BASE 0x1f2
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#define IA32_SMRR_PHYS_BASE 0x1f2
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#define IA32_SMRR_PHYS_MASK 0x1f3
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#define IA32_SMRR_PHYS_MASK 0x1f3
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/* Specific to model_6fx and model_1067x */
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#define MSR_SMRR_PHYS_BASE 0xa0
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#define MSR_SMRR_PHYS_MASK 0xa1
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#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
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#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
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#define MTRR_PHYS_MASK_VALID (1 << 11)
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#define MTRR_PHYS_MASK_VALID (1 << 11)
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