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soc/intel/skylake/acpi/dptf: Remove processor throttling controls 

The fwts method test reports errors on the methods implementing
processor throttling control. The T states are not supported in coreboot
at this moment.

Remove the methods required by processor throttling control. They can be
restored when the required support has been added to the SoC
implementation.

BUG=https://ticket.coreboot.org/issues/252
TEST=tested using fwts on facebook monolith.

Found-by: fwts 19.12.00
Change-Id: Ib50607f60cdb2ad03e613d18b40f56a4c4a4c714
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Wim Vervoorn 2019-12-23 16:16:18 +01:00 committed by Nico Huber
parent d5f0b4a17b
commit 06f855cfe9
1 changed files with 0 additions and 65 deletions
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65
src/soc/intel/skylake/acpi/dptf/cpu.asl
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@ -23,10 +23,6 @@
#endif
External (\_PR.CP00._PSS, PkgObj)
External (\_PR.CP00._TSS, PkgObj)
External (\_PR.CP00._TPC, MethodObj)
External (\_PR.CP00._PTC, PkgObj)
External (\_PR.CP00._TSD, PkgObj)
External (\_SB.MPDL, IntObj)
Device (B0D4)
@ -42,67 +38,6 @@ Device (B0D4)
}
}
/*
* Processor Throttling Controls
*/
Method (_TSS)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Return (\_PR.CP00._TSS)
} Else {
Return (Package ()
{
Package () { 0, 0, 0, 0, 0 }
})
}
}
Method (_TPC)
{
If (CondRefOf (\_PR.CP00._TPC)) {
Return (\_PR.CP00._TPC)
} Else {
Return (0)
}
}
Method (_PTC)
{
If (CondRefOf (\_PR.CP00._PTC)) {
Return (\_PR.CP00._PTC)
} Else {
Return (Package ()
{
Buffer () { 0 },
Buffer () { 0 }
})
}
}
Method (_TSD)
{
If (CondRefOf (\_PR.CP00._TSD)) {
Return (\_PR.CP00._TSD)
} Else {
Return (Package ()
{
Package () { 5, 0, 0, 0, 0 }
})
}
}
Method (_TDL)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Store (SizeOf (\_PR.CP00._TSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {
Return (0)
}
}
/*
* Processor Performance Control
*/