mb/google/poppy/variant/nami: Add TSR2 on DPTF
Add TSR2 DART/DTRT package BUG=b:110451144 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test image with dptf.dv Change-Id: I3328e17328415f5ebdcf84263e5456e11e55f769 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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@ -41,6 +41,16 @@
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#define DPTF_TSR1_ACTIVE_AC3 42
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#define DPTF_TSR1_ACTIVE_AC4 39
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Thermal_Sensor_Remote_CPU"
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#define DPTF_TSR2_PASSIVE 75
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#define DPTF_TSR2_CRITICAL 125
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#define DPTF_TSR2_ACTIVE_AC0 50
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#define DPTF_TSR2_ACTIVE_AC1 47
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#define DPTF_TSR2_ACTIVE_AC2 45
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#define DPTF_TSR2_ACTIVE_AC3 42
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#define DPTF_TSR2_ACTIVE_AC4 39
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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@ -91,6 +101,10 @@ Name (DART, Package () {
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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}
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})
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#endif
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@ -104,6 +118,9 @@ Name (DTRT, Package () {
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/* CPU Throttle Effect on TSR1 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 1, 0, 0, 0, 0 },
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/* CPU Throttle Effect on TSR2 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 1, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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