mods for early printing on OLPC
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
ab4f5d0c10
commit
070a10f759
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@ -89,7 +89,8 @@
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#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1)
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#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1)
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/* South Bridge*/
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#define MSR_SB (SB_PORT << 23) + MSR_PCI /* address to the SouthBridge*/
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#define SB_PORT 2 /* port of the SouthBridge */
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#define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* address to the SouthBridge*/
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#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/
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@ -502,7 +503,7 @@
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#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
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#define CHIPSET_DEV_NUM 15
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#define IDSEL_BASE 11 // bit 11 = device 1
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#define SB_PORT 2 // port of the SouthBridge
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/* standard AMD post definitions -- might as well use them. */
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#define POST_Output_Port (0x080) /* port to write post codes to*/
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@ -113,6 +113,24 @@ static void cs5536_setup_gpio(void)
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//outl(0x3ffbc004, 0x6100 + 0x34);
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outl(0x3fffc000, 0x6100 + 0x34);
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//outl(val, 0x6100 + 0x34);
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#if 0
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/* changes proposed by Ollie; we will test this later. */
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/* setup GPIO pins 14/15 for SDA/SCL */
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val = GPIOL_15_SET | GPIOL_14_SET;
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/* Output Enable */
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//outl(0x3fffc000, 0x6100 + 0x04);
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outl(val, 0x6100 + 0x04);
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/* Output AUX1 */
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//outl(0x3fffc000, 0x6100 + 0x10);
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outl(val, 0x6100 + 0x10);
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/* Input Enable */
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//outl(0x3fffc000, 0x6100 + 0x20);
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outl(val, 0x6100 + 0x20);
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/* Input AUX1 */
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//outl(0x3fffc000, 0x6100 + 0x34);
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outl(val, 0x6100 + 0x34);
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#endif
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}
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static void cs5536_disable_internal_uart(void)
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@ -158,7 +176,8 @@ static void dummy(void)
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/* see page 412 of the cs5536 companion book */
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static int cs5536_setup_onchipuart(void)
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{
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/* ToDo:
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unsigned long m;
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/*
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* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
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* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
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* 2. Enable UART IO space in MDD
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@ -171,8 +190,46 @@ static int cs5536_setup_onchipuart(void)
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msr_t msr;
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msr.lo = 2;
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msr.hi = 0;
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/* not sure what this is for, so comment it out ...
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wrmsr(0x5140003a, msr);
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wrmsr(0x5140003e, msr);
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*/
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/* GPIO8 - UART1_TX */
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/* Set: Output Enable (0x4) */
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m = inl(GPIOL_OUTPUT_ENABLE);
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m |= GPIOL_8_SET;
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m &= ~GPIOL_8_CLEAR;
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outl(m,GPIOL_OUTPUT_ENABLE);
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/* Set: OUTAUX1 Select (0x10) */
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m = inl(GPIOL_OUT_AUX1_SELECT);
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m |= GPIOL_8_SET;
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m &= ~GPIOL_8_CLEAR;
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outl(m,GPIOL_OUT_AUX1_SELECT);
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/* Set: Pull Up (0x18) */
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m = inl(GPIOL_PULLUP_ENABLE);
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m |= GPIOL_8_SET;
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m &= ~GPIOL_8_CLEAR;
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/* GPIO9 - UART1_RX */
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/* Set: Pull Up (0x18) */
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m |= GPIOL_9_SET;
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m &= ~GPIOL_9_CLEAR;
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outl(m,GPIOL_PULLUP_ENABLE);
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/* Set: Input Enable (0x20) */
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m = inl(GPIOL_INPUT_ENABLE);
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m |= GPIOL_9_SET;
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m &= ~GPIOL_9_CLEAR;
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outl(m,GPIOL_INPUT_ENABLE);
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/* Set: INAUX1 Select (0x34) */
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m = inl(GPIOL_IN_AUX1_SELECT);
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m |= GPIOL_9_SET;
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m &= ~GPIOL_9_CLEAR;
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outl(m,GPIOL_IN_AUX1_SELECT);
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msr = rdmsr(MDD_LEG_IO);
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msr.lo |= 0x7 << 16;
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wrmsr(MDD_LEG_IO,msr);
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}
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static int cs5536_early_setup(void)
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@ -5,17 +5,17 @@ mainboard olpc/rev_a
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option ROM_SIZE=1024*256
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romimage "normal"
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option USE_FALLBACK_IMAGE=0
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION=".0Normal"
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# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
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# payload ../../../../tg3--ide_disk.zelf
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# payload ../../../../../lnxieepro100.ebi
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# payload /etc/hosts
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# payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
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payload /tmp/filo.elf
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end
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#romimage "normal"
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# option USE_FALLBACK_IMAGE=0
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# option ROM_IMAGE_SIZE=0x10000
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# option LINUXBIOS_EXTRA_VERSION=".0Normal"
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## payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
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## payload ../../../../tg3--ide_disk.zelf
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## payload ../../../../../lnxieepro100.ebi
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## payload /etc/hosts
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## payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
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# payload /tmp/filo.elf
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#end
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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@ -29,4 +29,5 @@ romimage "fallback"
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payload /tmp/filo.elf
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end
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buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
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buildrom ./linuxbios.rom ROM_SIZE "fallback"
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#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
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