GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amd/stoneyridge: Add PSP definitions southbridge and iomap 

Define the PSP's BAR3 and BAR3 enable bit.  Define a default base
address for BAR3.

Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-10-30 14:52:01 -06:00 committed by Aaron Durbin
parent 5f0520a909
commit 07132a4c32
2 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/amd/stoneyridge/include/soc/iomap.h
View File

@ -18,6 +18,7 @@
#define __SOC_STONEYRIDGE_IOMAP_H__ #define __SOC_STONEYRIDGE_IOMAP_H__
/* MMIO Ranges */ /* MMIO Ranges */
#define PSP_MAILBOX_BAR3_BASE 0xf0a00000
#define SPI_BASE_ADDRESS 0xfec10000 #define SPI_BASE_ADDRESS 0xfec10000
#define IO_APIC2_ADDR 0xfec20000 #define IO_APIC2_ADDR 0xfec20000

6
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -21,9 +21,15 @@
#include <types.h> #include <types.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include "chip.h" #include "chip.h"
/* PSP at D8F0 */
#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
#define PSP_BAR_ENABLES 0x48
#define PSP_MAILBOX_BAR_EN 0x10
/* Power management index/data registers */ /* Power management index/data registers */
#define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5 #define BIOSRAM_DATA 0xcd5