soc/intel/broadwell: Relocate PCH finalisation code

Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46709
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 22:35:41 +02:00
parent 9eaca7dcf4
commit 071754c9dc
4 changed files with 56 additions and 43 deletions

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@ -4,15 +4,9 @@
#include <console/console.h> #include <console/console.h>
#include <console/post_codes.h> #include <console/post_codes.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/lpc.h> #include <soc/pch.h>
#include <soc/me.h>
#include <soc/rcba.h>
#include <soc/spi.h>
#include <soc/systemagent.h> #include <soc/systemagent.h>
#include <southbridge/intel/common/spi.h>
/* /*
* 16.6 System Agent Configuration Locking * 16.6 System Agent Configuration Locking
@ -55,48 +49,13 @@ static void broadwell_systemagent_finalize(void)
MCHBAR32(0x6008) = MCHBAR32(0x6008); MCHBAR32(0x6008) = MCHBAR32(0x6008);
} }
const struct reg_script pch_finalize_script[] = {
#if !CONFIG(EM100PRO_SPI_CONSOLE)
/* Lock SPIBAR */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
SPIBAR_HSFS_FLOCKDN),
#endif
/* TC Lockdown */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
/* BIOS Interface Lockdown */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
/* Function Disable SUS Well Lockdown */
REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
/* Global SMI Lock */
REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
/* GEN_PMCON Lock */
REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
/* PMSYNC */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
REG_SCRIPT_END
};
static void broadwell_finalize(void *unused) static void broadwell_finalize(void *unused)
{ {
printk(BIOS_DEBUG, "Finalizing chipset.\n"); printk(BIOS_DEBUG, "Finalizing chipset.\n");
broadwell_systemagent_finalize(); broadwell_systemagent_finalize();
spi_finalize_ops(); broadwell_pch_finalize();
reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
/* Lock */
RCBA32_OR(0x3a6c, 0x00000001);
/* Read+Write this R/WO register */
RCBA32(LCAP) = RCBA32(LCAP);
/* Indicate finalize step with post code */ /* Indicate finalize step with post code */
post_code(POST_OS_BOOT); post_code(POST_OS_BOOT);

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@ -30,4 +30,6 @@ int pch_is_wpt_ulx(void);
u32 pch_read_soft_strap(int id); u32 pch_read_soft_strap(int id);
void pch_disable_devfn(struct device *dev); void pch_disable_devfn(struct device *dev);
void broadwell_pch_finalize(void);
#endif #endif

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@ -3,6 +3,7 @@ bootblock-y += bootblock.c
ramstage-y += adsp.c ramstage-y += adsp.c
romstage-y += early_pch.c romstage-y += early_pch.c
ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += finalize.c
ramstage-y += gpio.c ramstage-y += gpio.c
romstage-y += gpio.c romstage-y += gpio.c
smm-y += gpio.c smm-y += gpio.c

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@ -0,0 +1,51 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
#include <soc/pch.h>
#include <soc/rcba.h>
#include <soc/spi.h>
#include <southbridge/intel/common/spi.h>
const struct reg_script pch_finalize_script[] = {
#if !CONFIG(EM100PRO_SPI_CONSOLE)
/* Lock SPIBAR */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
SPIBAR_HSFS_FLOCKDN),
#endif
/* TC Lockdown */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
/* BIOS Interface Lockdown */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
/* Function Disable SUS Well Lockdown */
REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
/* Global SMI Lock */
REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
/* GEN_PMCON Lock */
REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
/* PMSYNC */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
REG_SCRIPT_END
};
void broadwell_pch_finalize(void)
{
spi_finalize_ops();
reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
/* Lock */
RCBA32_OR(0x3a6c, 0x00000001);
/* Read+Write this R/WO register */
RCBA32(LCAP) = RCBA32(LCAP);
}