mb/intel/mtlrvp: Enable EC for mtlrvp

This patch will initialize EC for mtlrvp which includes,
1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC)
2. Add respective ACPI configuration
3. Add ec.c required for ramstage
4. Program EC ranges as part of devicetree.cb
5. Enable VBOOT in Kconfig

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with
CHROME_EC using subsequent patches in the train

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jamie Ryu 2022-07-22 12:29:57 -07:00 committed by Felix Held
parent 1201fb9a91
commit 071d7f3cef
8 changed files with 146 additions and 1 deletions

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@ -44,4 +44,27 @@ config OVERRIDE_DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
choice
prompt "ON BOARD EC"
default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P
default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC
help
This option allows you to select the on board EC to use.
Select whether the board has Intel EC or/and Chrome EC
config MTL_CHROME_EC
bool "Chrome EC"
select EC_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_BOARDID
config MTL_INTEL_EC
bool "Intel EC"
select EC_ACPI
endchoice
config VBOOT
select VBOOT_LID_SWITCH
endif # BOARD_INTEL_MTLRVP_COMMON

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@ -1,5 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-or-later
ramstage-y += ec.c
VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))

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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <baseboard/ec.h>
DefinitionBlock(
"dsdt.aml",
@ -24,5 +25,17 @@ DefinitionBlock(
}
}
#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
#endif
#include <southbridge/intel/common/acpi/sleepstates.asl>
}

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@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <baseboard/ec.h>
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
void mainboard_ec_init(void)
{
const struct google_chromeec_event_info info = {
.log_events = MAINBOARD_EC_LOG_EVENTS,
.sci_events = MAINBOARD_EC_SCI_EVENTS,
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
};
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
}

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@ -1,5 +1,11 @@
chip soc/intel/meteorlake
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
device domain 0 on
device ref igpu on end
end

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@ -0,0 +1,70 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_EC_H__
#define __BASEBOARD_EC_H__
#include <baseboard/gpio.h>
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/*
* EC can wake from S3 with lid or power button or key press or
* mode change event.
*/
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
/*
* ACPI related definitions for ASL code.
*/
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
/* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
#endif /* __BASEBOARD_EC_H__ */

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@ -6,4 +6,10 @@
#include <soc/gpe.h>
#include <soc/gpio.h>
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
#endif /* __BASEBOARD_GPIO_H__ */

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@ -1,4 +1,10 @@
chip soc/intel/meteorlake
device domain 0 on end
device domain 0 on
device ref soc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
end
end