mb/intel/mtlrvp: Enable EC for mtlrvp
This patch will initialize EC for mtlrvp which includes, 1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC) 2. Add respective ACPI configuration 3. Add ec.c required for ramstage 4. Program EC ranges as part of devicetree.cb 5. Enable VBOOT in Kconfig BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with CHROME_EC using subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -44,4 +44,27 @@ config OVERRIDE_DEVICETREE
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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choice
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prompt "ON BOARD EC"
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default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P
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default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC
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help
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This option allows you to select the on board EC to use.
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Select whether the board has Intel EC or/and Chrome EC
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config MTL_CHROME_EC
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bool "Chrome EC"
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select EC_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_BOARDID
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config MTL_INTEL_EC
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bool "Intel EC"
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select EC_ACPI
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endchoice
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config VBOOT
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select VBOOT_LID_SWITCH
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endif # BOARD_INTEL_MTLRVP_COMMON
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@ -1,5 +1,7 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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ramstage-y += ec.c
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VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
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BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <baseboard/ec.h>
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DefinitionBlock(
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"dsdt.aml",
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@ -24,5 +25,17 @@ DefinitionBlock(
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}
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}
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#endif
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <baseboard/ec.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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void mainboard_ec_init(void)
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{
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const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
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};
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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@ -1,5 +1,11 @@
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chip soc/intel/meteorlake
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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device domain 0 on
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device ref igpu on end
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end
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@ -0,0 +1,70 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_EC_H__
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#define __BASEBOARD_EC_H__
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#include <baseboard/gpio.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
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#define MAINBOARD_EC_SMI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
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/* EC can wake from S5 with lid or power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/*
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* EC can wake from S3 with lid or power button or key press or
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* mode change event.
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*/
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#define MAINBOARD_EC_S3_WAKE_EVENTS \
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(MAINBOARD_EC_S5_WAKE_EVENTS |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/* Enable LID switch and provide wake pin for EC */
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#define EC_ENABLE_LID_SWITCH
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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#endif /* __BASEBOARD_EC_H__ */
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@ -6,4 +6,10 @@
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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#endif /* __BASEBOARD_GPIO_H__ */
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@ -1,4 +1,10 @@
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chip soc/intel/meteorlake
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device domain 0 on end
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device domain 0 on
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device ref soc_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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end
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end
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