1. Remove warnings and multiple blank lines.

2. Mahogany uses GPIO9 to detect 80-pin IDE cable.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/mahogany/acpi_tables.c

@@ -101,6 +101,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 extern void get_bus_conf(void);
 
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 static void update_ssdtx(void *ssdtx, int i)
 {
 	uint8_t *PCI;
@@ -122,6 +123,7 @@ static void update_ssdtx(void *ssdtx, int i)
 	/* FIXME: need to update the GSI id in the ssdtx too */
 
 }
+#endif
 
 unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
 	k8acpi_write_vars();
@@ -140,6 +142,11 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	acpi_header_t const *p;
+	int i;
+#endif
 
 	get_bus_conf();		/* it will get sblk, pci1234, hcdn, and sbdn */
 

src/mainboard/amd/mahogany/devicetree.cb

@@ -121,4 +121,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #pci_domain
 end		#northbridge/amd/amdk8/root_complex
-

src/mainboard/amd/mahogany/get_bus_conf.c

@@ -63,6 +63,8 @@ extern void get_sblk_pci1234(void);
 
 static u32 get_bus_conf_done = 0;
 
+void get_bus_conf(void);
+
 void get_bus_conf(void)
 {
 	u32 apicid_base;

src/mainboard/amd/mahogany/mainboard.c

@@ -25,6 +25,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
+#include <arch/coreboot_tables.h>
 #include <../southbridge/amd/sb700/sb700.h>
 #include "chip.h"
 
@@ -35,6 +36,9 @@ extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
 
 uint64_t uma_memory_base, uma_memory_size;
 
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+
 /*
  * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
  * pull it up before training the slot.
@@ -65,12 +69,13 @@ void set_pcie_reset()
 	pci_write_config16(sm_dev, 0xA8, word);
 }
 
+#if 0	     /* not tested yet */
 /********************************************************
-* mahogany uses SB700 GPIO8 to detect IDE_DMA66.
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
 * get the cable type, 40 pin or 80 pin?
 ********************************************************/
-static void get_ide_dma66()
+static void get_ide_dma66(void)
 {
 	u8 byte;
 	/*u32 sm_dev, ide_dev; */
@@ -79,27 +84,29 @@ static void get_ide_dma66()
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	byte = pci_read_config8(sm_dev, 0xA9);
-	byte |= (1 << 4);	/* Set Gpio8 as input */
+	byte |= (1 << 5);	/* Set Gpio9 as input */
 	pci_write_config8(sm_dev, 0xA9, byte);
 
 	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 	byte = pci_read_config8(ide_dev, 0x56);
 	byte &= ~(7 << 0);
-	if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
+	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
 		byte |= 2 << 0;	/* mode 2 */
 	else
 		byte |= 5 << 0;	/* mode 5 */
 	pci_write_config8(ide_dev, 0x56, byte);
 }
+#endif	/* get_ide_dma66 */
 
 /*************************************************
 * enable the dedicated function in mahogany board.
 * This function called early than rs780_enable.
 *************************************************/
-void mahogany_enable(device_t dev)
+static void mahogany_enable(device_t dev)
 {
-	struct mainboard_config *mainboard =
+	/* Leave it for future. */
-	    (struct mainboard_config *)dev->chip_info;
+	/* struct mainboard_config *mainboard =
+	   (struct mainboard_config *)dev->chip_info;*/
 
 	printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
@@ -158,6 +165,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
 			    uma_memory_size);
 #endif
+	return 0;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/amd/mahogany_fam10/Kconfig

@@ -117,7 +117,7 @@ config HEAP_SIZE
 
 config ACPI_SSDTX_NUM
 	int
-	default 31
+	default 0
 	depends on BOARD_AMD_MAHOGANY_FAM10
 
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID

src/mainboard/amd/mahogany_fam10/acpi_tables.c

@@ -92,7 +92,8 @@ unsigned long acpi_fill_madt(unsigned long current)
 extern void get_bus_conf(void);
 extern void update_ssdt(void *ssdt);
 
-
+/* not tested yet. */
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 static void update_ssdtx(void *ssdtx, int i)
 {
 	u8 *PCI;
@@ -115,6 +116,7 @@ static void update_ssdtx(void *ssdtx, int i)
 	/* FIXME: need to update the GSI id in the ssdtx too */
 
 }
+#endif
 
 unsigned long write_acpi_tables(unsigned long start)
 {
@@ -129,10 +131,11 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 	acpi_header_t *ssdtx;
 	acpi_header_t const *p;
-
 	int i;
+#endif
 
 	get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
 
@@ -204,7 +207,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 	current = acpi_add_ssdt_pstates(rsdp, current);
 
-#if 0 //CONFIG_ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
 	/* same htio, but different possition? We may have to copy,
 	change HCIN, and recalculate the checknum and add_table */

src/mainboard/amd/mahogany_fam10/devicetree.cb

@@ -143,5 +143,3 @@ chip northbridge/amd/amdfam10/root_complex
 #	 end
 
 end
-
-

src/mainboard/amd/mahogany_fam10/mainboard.c

@@ -25,6 +25,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
+#include <arch/coreboot_tables.h>
 #include <../southbridge/amd/sb700/sb700.h>
 #include "chip.h"
 
@@ -35,6 +36,9 @@ extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
 
 uint64_t uma_memory_base, uma_memory_size;
 
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+
 /*
  * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
  * pull it up before training the slot.
@@ -65,12 +69,13 @@ void set_pcie_reset()
 	pci_write_config16(sm_dev, 0xA8, word);
 }
 
+#if 0	     /* not tested yet. */
 /********************************************************
-* mahogany uses SB700 GPIO8 to detect IDE_DMA66.
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
 * get the cable type, 40 pin or 80 pin?
 ********************************************************/
-static void get_ide_dma66()
+static void get_ide_dma66(void)
 {
 	u8 byte;
 	/*u32 sm_dev, ide_dev; */
@@ -79,27 +84,29 @@ static void get_ide_dma66()
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	byte = pci_read_config8(sm_dev, 0xA9);
-	byte |= (1 << 4);	/* Set Gpio8 as input */
+	byte |= (1 << 5);	/* Set Gpio9 as input */
 	pci_write_config8(sm_dev, 0xA9, byte);
 
 	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 	byte = pci_read_config8(ide_dev, 0x56);
 	byte &= ~(7 << 0);
-	if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
+	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
 		byte |= 2 << 0;	/* mode 2 */
 	else
 		byte |= 5 << 0;	/* mode 5 */
 	pci_write_config8(ide_dev, 0x56, byte);
 }
+#endif	/* get_ide_dma66() */
 
 /*************************************************
 * enable the dedicated function in mahogany board.
 * This function called early than rs780_enable.
 *************************************************/
-void mahogany_enable(device_t dev)
+static void mahogany_enable(device_t dev)
 {
-	struct mainboard_config *mainboard =
+	/* Leave it for furture use. */
-	    (struct mainboard_config *)dev->chip_info;
+	/* struct mainboard_config *mainboard =
+	   (struct mainboard_config *)dev->chip_info; */
 
 	printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
@@ -158,6 +165,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
 			    uma_memory_size);
 #endif
+	return 0;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -298,4 +298,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
-