From 07441b5ae6db1d171474b393d98d7da9595bcc8a Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 9 Mar 2017 10:59:25 -0800 Subject: [PATCH] soc/intel/apollolake: Wrap lines at 80 columns Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build for reef Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/18728 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/apollolake/acpi.c | 3 +- .../intel/apollolake/bootblock/cache_as_ram.S | 2 +- src/soc/intel/apollolake/chip.c | 4 +- src/soc/intel/apollolake/chip.h | 6 ++- src/soc/intel/apollolake/flash_ctrlr.c | 3 +- src/soc/intel/apollolake/gpio.c | 3 +- src/soc/intel/apollolake/include/FspUpd.h | 6 +-- .../apollolake/include/soc/flash_ctrlr.h | 3 +- .../intel/apollolake/include/soc/gpio_defs.h | 3 +- .../intel/apollolake/include/soc/pci_devs.h | 3 +- src/soc/intel/apollolake/include/soc/pm.h | 24 +++++----- src/soc/intel/apollolake/mmap_boot.c | 48 ++++++++++--------- src/soc/intel/apollolake/northbridge.c | 7 +-- src/soc/intel/apollolake/romstage.c | 6 ++- 14 files changed, 69 insertions(+), 52 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 8f9247579f..7c3f3136ad 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -64,7 +64,8 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); /* SCI */ - current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, + flags); return current; } diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 65dd4c83f9..495b61bfac 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -157,7 +157,7 @@ clear_var_mtrr: mov %eax, %ecx /* save to ecx */ mov $1, %ebx shl %cl, %ebx - sub $1, %ebx /* resulting mask is is in ebx */ + sub $1, %ebx /* resulting mask is is in ebx */ /* Set this mask for initial cache fill */ mov $MSR_L2_QOS_MASK(0), %ecx diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index eacf554105..2973abf8be 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -488,7 +488,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; - /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ + /* Disable monitor mwait since it is broken due to a hardware bug + * without a fix + */ silconfig->MonitorMwaitEnable = 0; silconfig->SkipMpInit = 1; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 051816ddde..3221be7ac8 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -62,14 +62,16 @@ struct soc_intel_apollolake_config { /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. - * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements. + * Each = 125pSec. */ uint32_t emmc_tx_data_cntl2; /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. - * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements. + * Each = 125pSec. */ uint32_t emmc_rx_cmd_data_cntl1; diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c index 5f7d8049b2..d0bc4fa813 100644 --- a/src/soc/intel/apollolake/flash_ctrlr.c +++ b/src/soc/intel/apollolake/flash_ctrlr.c @@ -68,7 +68,8 @@ static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx) } /* Read register from the SPI flash controller. 'reg' is the register offset. */ -static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, uint16_t reg) +static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, + uint16_t reg) { uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); return read32((void *)addr); diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index affba3db7f..7be126ef9c 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -159,7 +159,8 @@ void gpio_configure_pad(const struct pad_config *cfg) * This is done to preserve config1 size as unit16 in gpio.h. */ dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK; - dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) << PAD_CFG1_IOSSTATE_SHIFT; + dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) + << PAD_CFG1_IOSSTATE_SHIFT; iosf_write(comm->port, config_offset, cfg->config0); iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1); diff --git a/src/soc/intel/apollolake/include/FspUpd.h b/src/soc/intel/apollolake/include/FspUpd.h index a7114ce39e..d98c42e10b 100644 --- a/src/soc/intel/apollolake/include/FspUpd.h +++ b/src/soc/intel/apollolake/include/FspUpd.h @@ -37,11 +37,11 @@ are permitted provided that the following conditions are met: #pragma pack(push, 1) -#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ #pragma pack(pop) diff --git a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h index 5b9c6222b3..336ce5266f 100644 --- a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h +++ b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h @@ -50,7 +50,8 @@ #define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) #define SPIBAR_HSFSTS_WET (1 << 21) #define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) -#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) +#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) \ + & SPIBAR_HSFSTS_FCYCLE_MASK) #define SPIBAR_HSFSTS_FGO (1 << 16) #define SPIBAR_HSFSTS_FLOCKDN (1 << 15) #define SPIBAR_HSFSTS_FDV (1 << 14) diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 18b95c9c63..2fdf10f7f7 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -436,7 +436,8 @@ #define GPIO_COMM_SW_NAME "INT3452:03" /* Default configurations */ -#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) +#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP \ + | PAD_CFG0_MODE_FUNC(x)) #define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) #define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 572fd38100..3e4dcb235e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -23,7 +23,8 @@ #if !defined(__SIMPLE_DEVICE__) #include #include -#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, \ + func)) #define _PCI_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) #else #include diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d3299b8282..f754541bc2 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -68,17 +68,19 @@ #define SMI_EOS 1 #define SMI_GBL 0 -#define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */ -#define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */ -#define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */ -#define GPIO_EN (1 << SMI_GPIO) /* Enable GPIO SMI */ -#define BIOS_RLS (1 << SMI_BIOS_RLS) /* asserts SCI on bit set */ -#define SWSMI_TMR_EN (1 << SMI_SWSMI_TMR) /* start software smi timer on bit set */ -#define APMC_EN (1 << SMI_APMC) /* Writes to APM_CNT cause SMI# */ -#define SLP_SMI_EN (1 << SMI_SLP) /* Write to SLP_EN in PM1_CNT asserts SMI# */ -#define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */ -#define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */ -#define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */ +#define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */ +#define GPIO_EN (1 << SMI_GPIO) /* Enable GPIO SMI */ +#define BIOS_RLS (1 << SMI_BIOS_RLS) /* asserts SCI on bit set */ +/* start software smi timer on bit set */ +#define SWSMI_TMR_EN (1 << SMI_SWSMI_TMR) +#define APMC_EN (1 << SMI_APMC) /* Writes to APM_CNT cause SMI# */ +/* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define SLP_SMI_EN (1 << SMI_SLP) +#define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */ +#define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */ #define SMI_STS 0x44 /* Bits for SMI status */ diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 3213b09b23..a92fbb3fc8 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -30,29 +30,31 @@ * space. However, 256KiB right below 4GiB is decoded by read-only SRAM and not * boot media. * - * +----------------+ 0 - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * +------------+ | | - * | IFD | | | - * bios_start +---> +------------+--------------------------> +----------------+ 4GiB - bios_size - * ^ | | ^ | | - * | | | | | | - * | | | bios_mapped_size | BIOS | - * | | BIOS | | | | - * bios_size | | | | | - * | | | v | | - * | | +--------------------------> +----------------+ 4GiB - 256KiB - * v | | | Read only SRAM | - * bios_end +---> +------------+ +----------------+ 4GiB - * | Device ext | - * +------------+ + * +-----------+ 0 + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * +--------+ | | + * | IFD | | | + * bios_start +---> +--------+------------------> +-----------+ 4GiB - bios_size + * ^ | | ^ | | + * | | | | | | + * | | | bios_mapped_size | BIOS | + * | | BIOS | | | | + * bios_size | | | | | + * | | | v | | + * | | +------------------> +-----------+ 4GiB - 256KiB + * | | | | Read only | + * v | | | SRAM | + * bios_end +---> +--------+ +-----------+ 4GiB + * | Device | + * | ext | + * +--------+ * */ diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index e1b54ec393..6f92283c43 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -105,14 +105,15 @@ static int mc_add_dram_resources(device_t dev, int index) touud <<= 32; touud |= ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB); - /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ + /* 0 -> 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ ram_resource(dev, index++, 0, 640); /* 0xa0000 - 0xbffff: legacy VGA */ mmio_resource(dev, index++, 640, 128); - /* 0xc0000 -> 0xfffff: leave without e820 entry, as it has special uses */ - /* 0x100000 -> top_of_ram */ + /* 0xc0000 -> 0xfffff: leave without e820 entry, as it has special uses + * 0x100000 -> top_of_ram + */ base_k = 1024; size_k = (tseg / KiB) - base_k; ram_resource(dev, index++, base_k, size_k); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9a153b34f4..93b571e586 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -220,7 +220,8 @@ asmlinkage void car_stage_entry(void) top_of_ram = (uintptr_t) cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) @@ -244,7 +245,8 @@ asmlinkage void car_stage_entry(void) static void fill_console_params(FSPM_UPD *mupd) { if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { - mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; + mupd->FspmConfig.SerialDebugPortDevice = + CONFIG_UART_FOR_CONSOLE; /* use MMIO port type */ mupd->FspmConfig.SerialDebugPortType = 2; /* use 4 byte register stride */