mb/google/asurada: Init dram in romstage
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -8,6 +8,7 @@ verstage-y += reset.c
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romstage-y += memlayout.ld
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romstage-y += boardid.c
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romstage-y += romstage.c
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romstage-y += sdram_configs.c
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ramstage-y += memlayout.ld
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@ -0,0 +1,48 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/stages.h>
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#include <console/console.h>
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#include <fmap.h>
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#include <soc/dramc_param.h>
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#include <soc/emi.h>
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#include <soc/mmu_operations.h>
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/* This must be defined in chromeos.fmd in same name and size. */
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#define CALIBRATION_REGION "RW_DDR_TRAINING"
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#define CALIBRATION_REGION_SIZE 0x2000
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_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE,
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"sizeof(struct dramc_param) exceeds " CALIBRATION_REGION);
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static bool read_calibration_data_from_flash(struct dramc_param *dparam)
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{
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const size_t length = sizeof(*dparam);
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size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length);
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printk(BIOS_DEBUG, "read data from flash, ret=%#zx, length=%#zx\n", ret, length);
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return ret == length;
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}
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static bool write_calibration_data_to_flash(const struct dramc_param *dparam)
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{
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const size_t length = sizeof(*dparam);
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size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length);
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printk(BIOS_DEBUG, "write data from flash, ret=%#zx, length=%#zx\n", ret, length);
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return ret == length;
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}
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/* dramc_param is ~2K and too large to fit in stack. */
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static struct dramc_param dramc_parameter;
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static struct dramc_param_ops dparam_ops = {
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.param = &dramc_parameter,
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.read_from_flash = &read_calibration_data_from_flash,
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.write_to_flash = &write_calibration_data_to_flash,
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};
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void platform_romstage_main(void)
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{
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mt_mem_init(&dparam_ops);
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mtk_mmu_after_dram();
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}
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