nb/intel/sandybridge: Drop dead code
Sandy Bridge now uses the same code as Ivy Bridge. Drop the old code. Change-Id: I4f6a71a4223194d83c0ee790d317ecdcafd664fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Angel Pons
Patrick Georgi
parent
efbed263df
commit
07609028ec
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@ -23,7 +23,6 @@ ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
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romstage-y += early_dmi.c
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romstage-y += raminit.c
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romstage-y += raminit_common.c
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romstage-y += raminit_sandy.c
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romstage-y += raminit_ivy.c
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romstage-y += raminit_tables.c
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romstage-y += ../../../device/dram/ddr3.c
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@ -181,6 +181,4 @@ void final_registers(ramctr_timing *ctrl);
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void restore_timings(ramctr_timing *ctrl);
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int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size);
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int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size);
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#endif
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@ -1,470 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <console/console.h>
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#include <console/usb.h>
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#include <delay.h>
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#include "raminit_native.h"
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#include "raminit_common.h"
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#include "raminit_tables.h"
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/* Frequency multiplier */
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static u32 get_FRQ(u32 tCK)
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{
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const u32 FRQ = 256000 / (tCK * BASEFREQ);
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if (FRQ > 8)
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return 8;
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if (FRQ < 3)
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return 3;
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return FRQ;
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}
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/* Get REFI based on MC frequency */
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static u32 get_REFI(u32 tCK)
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{
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return frq_refi_map[0][get_FRQ(tCK) - 3];
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}
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/* Get XSOffset based on MC frequency */
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static u8 get_XSOffset(u32 tCK)
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{
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return frq_xs_map[0][get_FRQ(tCK) - 3];
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}
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/* Get MOD based on MC frequency */
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static u8 get_MOD(u32 tCK)
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{
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return frq_mod_map[0][get_FRQ(tCK) - 3];
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}
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/* Get Write Leveling Output delay based on MC frequency */
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static u8 get_WLO(u32 tCK)
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{
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return frq_wlo_map[0][get_FRQ(tCK) - 3];
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}
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/* Get CKE based on MC frequency */
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static u8 get_CKE(u32 tCK)
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{
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return frq_cke_map[0][get_FRQ(tCK) - 3];
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}
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/* Get XPDLL based on MC frequency */
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static u8 get_XPDLL(u32 tCK)
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{
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return frq_xpdll_map[0][get_FRQ(tCK) - 3];
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}
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/* Get XP based on MC frequency */
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static u8 get_XP(u32 tCK)
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{
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return frq_xp_map[0][get_FRQ(tCK) - 3];
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}
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/* Get AONPD based on MC frequency */
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static u8 get_AONPD(u32 tCK)
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{
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return frq_aonpd_map[0][get_FRQ(tCK) - 3];
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}
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/* Get COMP2 based on MC frequency */
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static u32 get_COMP2(u32 tCK)
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{
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return frq_comp2_map[0][get_FRQ(tCK) - 3];
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}
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static void snb_normalize_tclk(u32 *tclk)
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{
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if (*tclk <= TCK_1066MHZ) {
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*tclk = TCK_1066MHZ;
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} else if (*tclk <= TCK_933MHZ) {
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*tclk = TCK_933MHZ;
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} else if (*tclk <= TCK_800MHZ) {
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*tclk = TCK_800MHZ;
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} else if (*tclk <= TCK_666MHZ) {
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*tclk = TCK_666MHZ;
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} else if (*tclk <= TCK_533MHZ) {
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*tclk = TCK_533MHZ;
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} else if (*tclk <= TCK_400MHZ) {
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*tclk = TCK_400MHZ;
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} else {
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*tclk = 0;
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}
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}
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static void find_cas_tck(ramctr_timing *ctrl)
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{
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u8 val;
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/* Find CAS latency */
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while (1) {
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/*
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* Normalising tCK before computing clock could potentially
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* result in a lower selected CAS, which is desired.
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*/
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snb_normalize_tclk(&(ctrl->tCK));
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if (!(ctrl->tCK))
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die("Couldn't find compatible clock / CAS settings\n");
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val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
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printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK);
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for (; val <= MAX_CAS; val++)
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if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1)
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break;
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if (val == (MAX_CAS + 1)) {
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ctrl->tCK++;
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continue;
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} else {
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printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n");
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break;
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}
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}
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printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
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printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val);
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ctrl->CAS = val;
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}
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static void dram_timing(ramctr_timing *ctrl)
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{
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/*
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* On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133).
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* Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency.
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*/
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if (ctrl->tCK == TCK_1066MHZ) {
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ctrl->edge_offset[0] = 16;
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ctrl->edge_offset[1] = 7;
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ctrl->edge_offset[2] = 7;
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ctrl->timC_offset[0] = 18;
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ctrl->timC_offset[1] = 7;
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ctrl->timC_offset[2] = 7;
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ctrl->pi_coding_threshold = 13;
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} else if (ctrl->tCK == TCK_933MHZ) {
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ctrl->edge_offset[0] = 14;
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ctrl->edge_offset[1] = 6;
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ctrl->edge_offset[2] = 6;
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ctrl->timC_offset[0] = 15;
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ctrl->timC_offset[1] = 6;
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ctrl->timC_offset[2] = 6;
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ctrl->pi_coding_threshold = 15;
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} else if (ctrl->tCK == TCK_800MHZ) {
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ctrl->edge_offset[0] = 13;
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ctrl->edge_offset[1] = 5;
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ctrl->edge_offset[2] = 5;
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ctrl->timC_offset[0] = 14;
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ctrl->timC_offset[1] = 5;
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ctrl->timC_offset[2] = 5;
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ctrl->pi_coding_threshold = 15;
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} else if (ctrl->tCK == TCK_666MHZ) {
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ctrl->edge_offset[0] = 10;
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ctrl->edge_offset[1] = 4;
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ctrl->edge_offset[2] = 4;
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ctrl->timC_offset[0] = 11;
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ctrl->timC_offset[1] = 4;
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ctrl->timC_offset[2] = 4;
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ctrl->pi_coding_threshold = 16;
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} else if (ctrl->tCK == TCK_533MHZ) {
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ctrl->edge_offset[0] = 8;
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ctrl->edge_offset[1] = 3;
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ctrl->edge_offset[2] = 3;
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ctrl->timC_offset[0] = 9;
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ctrl->timC_offset[1] = 3;
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ctrl->timC_offset[2] = 3;
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ctrl->pi_coding_threshold = 17;
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} else {
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ctrl->tCK = TCK_400MHZ;
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ctrl->edge_offset[0] = 6;
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ctrl->edge_offset[1] = 2;
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ctrl->edge_offset[2] = 2;
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ctrl->timC_offset[0] = 6;
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ctrl->timC_offset[1] = 2;
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ctrl->timC_offset[2] = 2;
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ctrl->pi_coding_threshold = 17;
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}
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/* Initial phase between CLK/CMD pins */
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ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66;
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/* DLL_CONFIG_MDLL_W_TIMER */
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ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3;
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if (ctrl->tCWL)
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ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
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else
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ctrl->CWL = get_CWL(ctrl->tCK);
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printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL);
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/* Find tRCD */
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ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD);
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ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP);
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/* Find tRAS */
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ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS);
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/* Find tWR */
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ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR);
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/* Find tFAW */
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ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW);
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/* Find tRRD */
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ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD);
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/* Find tRTP */
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ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP);
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/* Find tWTR */
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ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR);
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/* Refresh-to-Active or Refresh-to-Refresh (tRFC) */
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ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
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printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
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ctrl->tREFI = get_REFI(ctrl->tCK);
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ctrl->tMOD = get_MOD(ctrl->tCK);
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ctrl->tXSOffset = get_XSOffset(ctrl->tCK);
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ctrl->tWLO = get_WLO(ctrl->tCK);
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ctrl->tCKE = get_CKE(ctrl->tCK);
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ctrl->tXPDLL = get_XPDLL(ctrl->tCK);
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ctrl->tXP = get_XP(ctrl->tCK);
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ctrl->tAONPD = get_AONPD(ctrl->tCK);
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}
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static void dram_freq(ramctr_timing *ctrl)
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{
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if (ctrl->tCK > TCK_400MHZ) {
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printk(BIOS_ERR,
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"DRAM frequency is under lowest supported frequency (400 MHz). "
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"Increasing to 400 MHz as last resort");
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ctrl->tCK = TCK_400MHZ;
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}
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while (1) {
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u8 val2;
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u32 reg1 = 0;
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/* Step 1 - Set target PCU frequency */
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find_cas_tck(ctrl);
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/* Frequency multiplier */
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const u32 FRQ = get_FRQ(ctrl->tCK);
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/*
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* The PLL will never lock if the required frequency is already set.
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* Exit early to prevent a system hang.
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*/
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reg1 = MCHBAR32(MC_BIOS_DATA);
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val2 = (u8) reg1;
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if (val2)
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return;
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/* Step 1 - Select frequency in the MCU */
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reg1 = FRQ;
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reg1 |= 0x80000000; /* set running bit */
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MCHBAR32(MC_BIOS_REQ) = reg1;
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int i=0;
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printk(BIOS_DEBUG, "PLL busy... ");
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while (reg1 & 0x80000000) {
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udelay(10);
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i++;
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reg1 = MCHBAR32(MC_BIOS_REQ);
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}
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printk(BIOS_DEBUG, "done in %d us\n", i * 10);
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/* Step 2 - Verify lock frequency */
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reg1 = MCHBAR32(MC_BIOS_DATA);
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val2 = (u8) reg1;
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if (val2 >= FRQ) {
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printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n",
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(1000 << 8) / ctrl->tCK);
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return;
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}
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printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n");
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ctrl->tCK++;
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}
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}
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static void dram_ioregs(ramctr_timing *ctrl)
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{
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u32 reg;
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int channel;
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/* IO clock */
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FOR_ALL_CHANNELS {
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MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel];
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}
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/* IO command */
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FOR_ALL_CHANNELS {
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MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel];
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}
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/* IO control */
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FOR_ALL_POPULATED_CHANNELS {
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program_timings(ctrl, channel);
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}
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/* Perform RCOMP */
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printram("RCOMP...");
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while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16)))
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;
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printram("done\n");
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/* Set COMP2 */
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MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK);
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printram("COMP2 done\n");
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/* Set COMP1 */
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FOR_ALL_POPULATED_CHANNELS {
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reg = MCHBAR32(CRCOMPOFST1_ch(channel));
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reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */
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reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */
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reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */
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MCHBAR32(CRCOMPOFST1_ch(channel)) = reg;
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}
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printram("COMP1 done\n");
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printram("FORCE RCOMP and wait 20us...");
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MCHBAR32(M_COMP) |= (1 << 8);
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udelay(20);
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printram("done\n");
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}
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int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size)
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{
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int err;
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printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", fast_boot);
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if (!fast_boot) {
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/* Find fastest common supported parameters */
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dram_find_common_params(ctrl);
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dram_dimm_mapping(ctrl);
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}
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/* Set MC frequency */
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dram_freq(ctrl);
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if (!fast_boot) {
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/* Calculate timings */
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dram_timing(ctrl);
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}
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/* Set version register */
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MCHBAR32(MRC_REVISION) = 0xc04eb002;
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/* Enable crossover */
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dram_xover(ctrl);
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/* Set timing and refresh registers */
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dram_timing_regs(ctrl);
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/* Power mode preset */
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MCHBAR32(PM_THML_STAT) = 0x5500;
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/* Set scheduler chicken bits */
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MCHBAR32(SCHED_CBIT) = 0x10100005;
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/* Set up watermarks and starvation counter */
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set_wmm_behavior(ctrl->cpu);
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/* Clear IO reset bit */
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MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5);
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/* Set MAD-DIMM registers */
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dram_dimm_set_mapping(ctrl);
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printk(BIOS_DEBUG, "Done dimm mapping\n");
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/* Zone config */
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dram_zones(ctrl, 1);
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/* Set memory map */
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dram_memorymap(ctrl, me_uma_size);
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printk(BIOS_DEBUG, "Done memory map\n");
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/* Set IO registers */
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dram_ioregs(ctrl);
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printk(BIOS_DEBUG, "Done io registers\n");
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udelay(1);
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if (fast_boot) {
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restore_timings(ctrl);
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} else {
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/* Do JEDEC DDR3 reset sequence */
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dram_jedecreset(ctrl);
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printk(BIOS_DEBUG, "Done jedec reset\n");
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/* MRS commands */
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dram_mrscommands(ctrl);
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printk(BIOS_DEBUG, "Done MRS commands\n");
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/* Prepare for memory training */
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prepare_training(ctrl);
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err = read_training(ctrl);
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if (err)
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return err;
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err = write_training(ctrl);
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if (err)
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return err;
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printram("CP5a\n");
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err = discover_edges(ctrl);
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if (err)
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return err;
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printram("CP5b\n");
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||||
err = command_training(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
printram("CP5c\n");
|
||||
|
||||
err = discover_edges_write(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = discover_timC_write(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
normalize_training(ctrl);
|
||||
}
|
||||
|
||||
set_read_write_timings(ctrl);
|
||||
|
||||
write_controller_mr(ctrl);
|
||||
|
||||
if (!s3_resume) {
|
||||
err = channel_test(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue