soc/mediatek/mt8183: Run DRAM full calibration
Load the calibration params from flash first and check the correctness of the params. If the params have correct format, perform DRAM fast calibration with these params to reduce bootup time. Otherwise, load the DRAM blob and perform DRAM full calibration. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Huayang Duan
Patrick Georgi
parent
846be446d3
commit
078332e4d8
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@ -14,6 +14,9 @@
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*/
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#include <arch/stages.h>
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#include <console/console.h>
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#include <fmap.h>
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#include <soc/dramc_param.h>
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#include <soc/emi.h>
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#include <soc/mmu_operations.h>
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#include <soc/mt6358.h>
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@ -22,6 +25,42 @@
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#include "early_init.h"
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/* This must be defined in chromeos.fmd in same name and size. */
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#define CALIBRATION_REGION "RW_DDR_TRAINING"
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#define CALIBRATION_REGION_SIZE 0x2000
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_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE,
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"sizeof(struct dramc_param) exceeds " CALIBRATION_REGION);
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static bool read_calibration_data_from_flash(struct dramc_param *dparam)
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{
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const size_t length = sizeof(*dparam);
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size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length);
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printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n",
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__func__, ret, length);
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return ret == length;
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}
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static bool write_calibration_data_to_flash(const struct dramc_param *dparam)
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{
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const size_t length = sizeof(*dparam);
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size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length);
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printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n",
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__func__, ret, length);
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return ret == length;
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}
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/* dramc_param is ~2K and too large to fit in stack. */
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static struct dramc_param dramc_parameter;
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static struct dramc_param_ops dparam_ops = {
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.param = &dramc_parameter,
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.read_from_flash = &read_calibration_data_from_flash,
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.write_to_flash = &write_calibration_data_to_flash,
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};
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void platform_romstage_main(void)
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{
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/* This will be done in verstage if CONFIG_VBOOT is enabled. */
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@ -34,6 +73,6 @@ void platform_romstage_main(void)
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mt_pll_raise_ca53_freq(1989 * MHz);
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pmic_init_scp_voltage();
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rtc_boot();
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mt_mem_init(get_sdram_config());
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mt_mem_init(&dparam_ops);
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mtk_mmu_after_dram();
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}
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@ -81,6 +81,14 @@ sspm.bin-file := $(MT8183_BLOB_DIR)/sspm.bin
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sspm.bin-type := raw
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sspm.bin-compression := $(CBFS_COMPRESS_FLAG)
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DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
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$(DRAM_CBFS)-file := $(MT8183_BLOB_DIR)/dram.elf
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$(DRAM_CBFS)-type := stage
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$(DRAM_CBFS)-compression := none
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ifneq ($(wildcard $($(DRAM_CBFS)-file)),)
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cbfs-files-y += $(DRAM_CBFS)
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endif
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BL31_MAKEARGS += PLAT=mt8183
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CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
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@ -71,6 +71,8 @@ struct sdram_params {
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u16 delay_cell_unit;
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};
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struct dramc_param_ops;
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enum {
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LP4X_DDR1600,
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LP4X_DDR2400,
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@ -86,6 +88,6 @@ size_t sdram_size(void);
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const struct sdram_params *get_sdram_config(void);
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void enable_emi_dcm(void);
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void mt_set_emi(const struct sdram_params *freq_params);
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void mt_mem_init(const struct sdram_params *freq_params);
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void mt_mem_init(struct dramc_param_ops *dparam_ops);
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#endif /* SOC_MEDIATEK_MT8183_EMI_H */
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@ -14,18 +14,18 @@
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*/
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#include <assert.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <soc/dramc_param.h>
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#include <soc/dramc_pi_api.h>
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#include <soc/emi.h>
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#include <string.h>
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#include <symbols.h>
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void mt_mem_init(const struct sdram_params *freq_params)
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static void mt_mem_test(void)
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{
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u64 rank_size[RANK_MAX];
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/* memory calibration */
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mt_set_emi(freq_params);
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if (CONFIG(MEMORY_TEST)) {
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size_t r;
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u8 *addr = _dram;
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@ -49,3 +49,132 @@ void mt_mem_init(const struct sdram_params *freq_params)
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}
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}
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}
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static void dump_param_header(const struct dramc_param *dparam)
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{
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const struct dramc_param_header *header = &dparam->header;
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printk(BIOS_DEBUG, "header.status = %#x\n", header->status);
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printk(BIOS_DEBUG, "header.magic = %#x (expected: %#x)\n",
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header->magic, DRAMC_PARAM_HEADER_MAGIC);
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printk(BIOS_DEBUG, "header.version = %#x (expected: %#x)\n",
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header->version, DRAMC_PARAM_HEADER_VERSION);
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printk(BIOS_DEBUG, "header.size = %#x (expected: %#lx)\n",
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header->size, sizeof(*dparam));
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printk(BIOS_DEBUG, "header.config = %#x\n", header->config);
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printk(BIOS_DEBUG, "header.flags = %#x\n", header->flags);
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printk(BIOS_DEBUG, "header.checksum = %#x\n", header->checksum);
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}
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static int dram_run_fast_calibration(const struct dramc_param *dparam,
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u16 config)
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{
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if (!is_valid_dramc_param(dparam)) {
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printk(BIOS_WARNING,
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"Invalid DRAM calibration data from flash\n");
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dump_param_header(dparam);
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return -1;
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}
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if (dparam->header.config != config) {
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printk(BIOS_WARNING,
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"Incompatible config for calibration data from flash "
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"(expected: %#x, saved: %#x)\n",
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config, dparam->header.config);
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return -1;
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}
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return 0;
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}
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static int dram_run_full_calibration(struct dramc_param *dparam, u16 config)
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{
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initialize_dramc_param(dparam, config);
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/* Load and run the provided blob for full-calibration if available */
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struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram");
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if (prog_locate(&dram))
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return -1;
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if (cbfs_prog_stage_load(&dram))
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return -2;
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prog_set_entry(&dram, prog_entry(&dram), dparam);
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prog_run(&dram);
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if (dparam->header.status != DRAMC_SUCCESS) {
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printk(BIOS_ERR, "Full calibration failed: status = %d\n",
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dparam->header.status);
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return -3;
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}
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if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) {
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printk(BIOS_ERR,
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"Full calibration executed without saving parameters. "
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"Please ensure the blob is built properly.\n");
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return -4;
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}
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return 0;
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}
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static void set_source_to_flash(struct sdram_params *freq_params)
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{
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for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX;
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shuffle++)
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freq_params[shuffle].source = DRAMC_PARAM_SOURCE_FLASH;
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}
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static void init_sdram_params(struct sdram_params *dst,
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const struct sdram_params *src)
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{
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for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX;
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shuffle++)
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memcpy(&dst[shuffle], src, sizeof(*dst));
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}
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void mt_mem_init(struct dramc_param_ops *dparam_ops)
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{
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struct dramc_param *dparam = dparam_ops->param;
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struct sdram_params *freq_params = dparam->freq_params;
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u16 config = 0;
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if (CONFIG(MT8183_DRAM_EMCP))
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config |= DRAMC_CONFIG_EMCP;
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/* Load calibration params from flash and run fast calibration */
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if (dparam_ops->read_from_flash(dparam)) {
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if (dram_run_fast_calibration(dparam, config) == 0) {
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printk(BIOS_INFO,
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"DRAM calibraion params loaded from flash\n");
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mt_set_emi(freq_params);
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mt_mem_test();
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return;
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}
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} else {
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printk(BIOS_WARNING,
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"Failed to read calibration data from flash\n");
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}
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/* Run full calibration */
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int err = dram_run_full_calibration(dparam, config);
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if (err == 0) {
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printk(BIOS_INFO, "Successfully loaded DRAM blobs and "
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"ran DRAM calibration\n");
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set_source_to_flash(dparam->freq_params);
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dparam_ops->write_to_flash(dparam);
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printk(BIOS_DEBUG, "Calibration params saved to flash: "
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"version=%#x, size=#%x\n",
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dparam->header.version, dparam->header.size);
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return;
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}
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printk(BIOS_ERR, "Failed to do full calibration (%d), "
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"falling back to load default sdram param\n", err);
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/* Init params from sdram configs and run partial calibration */
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init_sdram_params(freq_params, get_sdram_config());
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mt_set_emi(freq_params);
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mt_mem_test();
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}
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