GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/ec: Drop __PRE_RAM__ and __SMM__ guards 

For files built in ramstage and smm -classes, testing
for !__PRE_RAM__ is redundant.

All chip_operations are exluded with use of DEVTREE_EARLY
in static devicetree, so garbage collection will take care
of the !__SMM__ cases.

Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-08-17 15:14:38 +03:00
parent 7d640e2ac7
commit 07841c2a2a
9 changed files with 1 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/ec/acpi/ec.c
View File

@ -172,8 +172,6 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg)
#endif
#if !defined(__SMM__) && !defined(__PRE_RAM__)
struct chip_operations ec_acpi_ops = {
CHIP_NAME("ACPI Embedded Controller")
};
#endif

5
src/ec/compal/ene932/ec.c
View File

@ -14,8 +14,6 @@
* GNU General Public License for more details.
*/
#ifndef __PRE_RAM__
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
@ -125,7 +123,6 @@ static u8 ec_io_read(u16 addr)
}
*/
#ifndef __SMM__
static void ene932_init(struct device *dev)
{
if (!dev->enabled)
@ -155,5 +152,3 @@ struct chip_operations ec_compal_ene932_ops = {
CHIP_NAME("COMPAL ENE932 EC")
.enable_dev = enable_dev
};
#endif /* ! __SMM__ */
#endif /* ! __PRE_RAM__ */

4
src/ec/google/chromeec/ec.c
View File

@ -719,8 +719,6 @@ retry:
return cec_cmd.cmd_code;
}
#ifndef __PRE_RAM__
int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen,
uint8_t *buffer, int len, int is_read)
{
@ -1109,8 +1107,6 @@ int google_ec_running_ro(void)
return (ec_image_type == EC_IMAGE_RO);
}
#endif /* ! __PRE_RAM__ */
/**
* Check if EC/TCPM is in an alternate mode or not.
*

2
src/ec/google/chromeec/ec_i2c.c
View File

@ -252,10 +252,8 @@ int google_chromeec_command(struct chromeec_command *cec_command)
#endif /* CONFIG_EC_GOOGLE_CHROMEEC_I2C_PROTO3 */
#ifndef __PRE_RAM__
u8 google_chromeec_get_event(void)
{
printk(BIOS_ERR, "%s: Not supported.\n", __func__);
return 0;
}
#endif

5
src/ec/google/chromeec/ec_lpc.c
View File

@ -415,8 +415,6 @@ int google_chromeec_command(struct chromeec_command *cec_command)
return -1;
}
#ifndef __PRE_RAM__
#ifndef __SMM__
static void lpc_ec_init(struct device *dev)
{
if (!dev->enabled)
@ -471,8 +469,6 @@ struct chip_operations ec_google_chromeec_ops = {
.enable_dev = enable_dev,
};
#endif /* __SMM__ */
static int google_chromeec_data_ready(u16 port)
{
return google_chromeec_status_check(port, EC_LPC_CMDR_DATA,
@ -502,4 +498,3 @@ u8 google_chromeec_get_event(void)
/* Event (or 0 if none) is returned directly in the data byte */
return read_byte(EC_LPC_ADDR_ACPI_DATA);
}
#endif

2
src/ec/google/chromeec/ec_spi.c
View File

@ -115,10 +115,8 @@ int google_chromeec_command(struct chromeec_command *cec_command)
return crosec_command_proto(cec_command, crosec_spi_io, &slave);
}
#ifndef __PRE_RAM__
u8 google_chromeec_get_event(void)
{
printk(BIOS_ERR, "%s: Not supported.\n", __func__);
return 0;
}
#endif

5
src/ec/quanta/ene_kb3940q/ec.c
View File

@ -14,8 +14,6 @@
* GNU General Public License for more details.
*/
#ifndef __PRE_RAM__
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
@ -125,7 +123,6 @@ void ec_mem_write(u8 addr, u8 data)
return;
}
#ifndef __SMM__
static void ene_kb3940q_log_events(void)
{
#if CONFIG(ELOG)
@ -165,5 +162,3 @@ struct chip_operations ec_quanta_ene_kb3940q_ops = {
CHIP_NAME("QUANTA EnE KB3940Q EC")
.enable_dev = enable_dev
};
#endif /* ! __SMM__ */
#endif /* ! __PRE_RAM__ */

4
src/ec/quanta/it8518/ec.c
View File

@ -124,7 +124,6 @@ void ec_write(u16 addr, u8 data)
ec_write_ib(data);
}
#ifndef __PRE_RAM__
u8 ec_it8518_get_event(void)
{
@ -149,7 +148,6 @@ void ec_it8518_enable_wake_events(void)
ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE);
}
#ifndef __SMM__
static void it8518_init(struct device *dev)
{
if (!dev->enabled)
@ -178,5 +176,3 @@ struct chip_operations ec_quanta_it8518_ops = {
CHIP_NAME("QUANTA IT8518 EC")
.enable_dev = enable_dev
};
#endif /* ! __SMM__ */
#endif /* ! __PRE_RAM__ */

4
src/ec/smsc/mec1308/ec.c
View File

@ -115,10 +115,9 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg)
ec_data_reg = data_reg;
}
#if !defined(__PRE_RAM__) && !defined(__SMM__)
static void mec1308_enable(struct device *dev)
{
struct ec_smsc_mec1308_config *conf = dev->chip_info;
DEVTREE_CONST struct ec_smsc_mec1308_config *conf = dev->chip_info;
if (conf->mailbox_port) {
ec_cmd_reg = conf->mailbox_port;
@ -130,4 +129,3 @@ struct chip_operations ec_smsc_mec1308_ops = {
CHIP_NAME("SMSC MEC1308 EC Mailbox Interface")
.enable_dev = mec1308_enable
};
#endif