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vc/amd/pi/00630F01: Remove unused directory and code 

No board currently uses AMD PI 00630F01 so remove it.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3f990e44e0f769219a6f80cf1369f6a3c94b3509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2021-05-09 17:23:17 +02:00 committed by Marshall Dawson
parent 43d8eca2ba
commit 078448296c
36 changed files with 2 additions and 17356 deletions
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3641
src/vendorcode/amd/pi/00630F01/AGESA.h
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src/vendorcode/amd/pi/00630F01/AMD.h
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/* $NoKeywords:$ */
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _AMD_H_
#define _AMD_H_
#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
#define AGESA_REVISION "Arch2008"
#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
//
//
// AGESA Types and Definitions
//
//
#define LAST_ENTRY 0xFFFFFFFFul
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
#define IOCF8 0xCF8
#define IOCFC 0xCFC
/// The return status for all AGESA public services.
///
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
/// will have log entries with more detail.
///
typedef enum {
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
///< Not logged.
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
///< Example, memory address not installed, heap buffer handle not found.
///< Not Logged.
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT, ///< An observed condition, but no loss of function. See Log.
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
///< may not be able to reliably produce log events.
AgesaStatusMax ///< Not a status, for limit checking.
} AGESA_STATUS;
/// For checking whether a status is at or above the mandatory log level.
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
/**
* Callout method to the host environment.
*
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
*
* @param[in] Function The specific callout function being invoked.
* @param[in] FcnData Function specific data item.
* @param[in,out] ConfigPtr Reference to Callout params.
*/
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
IN UINT32 Function,
IN UINTN FcnData,
IN OUT VOID *ConfigPtr
);
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point
typedef enum {
PreMemHeap = 0, ///< Create heap in cache.
PostMemDram, ///< Create heap in memory.
ByHost ///< Create heap by Host.
} ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size
typedef enum ACCESS_WIDTH {
AccessWidth8 = 1, ///< Access width is 8 bits.
AccessWidth16, ///< Access width is 16 bits.
AccessWidth32, ///< Access width is 32 bits.
AccessWidth64, ///< Access width is 64 bits.
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
AccessS3SaveWidth16, ///< Save 16 bits data.
AccessS3SaveWidth32, ///< Save 32 bits data.
AccessS3SaveWidth64, ///< Save 64 bits data.
} ACCESS_WIDTH;
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
AMD_S3_SAVE = 0x0002C000, ///< AmdS3Save entry point handle
AMD_GET_APIC_ID = 0x0002D000, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS = 0x0002E000, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE = 0x0002F000, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG = 0x00030000, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE = 0x00031000, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK = 0x00032000, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle
AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle
AMD_S3FINAL_RESTORE = 0x00035000, ///< AmdS3FinalRestore entry point handle
AMD_INIT_RTB = 0x00036000, /* reserved */
AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
FCH_INIT_RESET = 0x00040000,
FCH_INIT_ENV = 0x00041000,
FCH_INIT_MID = 0x00042000,
FCH_INIT_LATE = 0x00043000,
FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
FCH_INIT_S3_LATE_RESTORE = 0x00045000,
AMD_SET_VALUE_invalid = 0x00081000,
AMD_GET_VALUE_invalid = 0x00082000,
} AGESA_STRUCT_NAME;
/* ResetType constant values */
#define WARM_RESET_WHENEVER 1
#define COLD_RESET_WHENEVER 2
#define WARM_RESET_IMMEDIATELY 3
#define COLD_RESET_IMMEDIATELY 4
// AGESA Structures
/// The standard header for all AGESA services.
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
typedef struct {
IN VOID * ImageBasePtr; ///< The AGESA Image base address.
IN UINT32 Func; ///< The service desired
IN VOID * AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN UINT64 HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// Create Struct Interface.
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
IN OUT VOID *NewStructPtr; ///< The struct for the service.
///< The struct to init for ByHost allocation,
///< the initialized struct on return.
} AMD_INTERFACE_PARAMS;
#define FUNC_0 0 // bit-placed for PCI address creation
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
/// AGESA Binary module header structure
typedef struct {
IN UINT32 Signature; ///< Binary Signature
IN CHAR8 CreatorID[8]; ///< 8 characters ID
IN CHAR8 Version[12]; ///< 12 characters version
IN UINT32 ModuleInfoOffset; ///< Offset of module
IN UINT32 EntryPointAddress; ///< Entry address
IN UINT32 ImageBase; ///< Image base
IN UINT32 RelocTableOffset; ///< Relocate Table offset
IN UINT32 ImageSize; ///< Size
IN UINT16 Checksum; ///< Checksum
IN UINT8 ImageType; ///< Type
IN UINT8 V_Reserved; ///< Reserved
} AMD_IMAGE_HEADER;
/// AGESA Binary module header structure
typedef struct _AMD_MODULE_HEADER {
IN UINT32 ModuleHeaderSignature; ///< Module signature
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
} AMD_MODULE_HEADER;
// AMD_CODE_HEADER Signatures.
#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
/// AGESA_CODE_SIGNATURE
typedef struct {
IN CHAR8 Signature[8]; ///< code header Signature
IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
IN CHAR8 Version[12]; ///< 12 character version string
IN CHAR8 TerminatorNull; ///< null terminated string
IN CHAR8 VerReserved[7]; ///< reserved space
} AMD_CODE_HEADER;
/// Extended PCI address format
typedef struct {
IN OUT UINT32 Register:12; ///< Register offset
IN OUT UINT32 Function:3; ///< Function number
IN OUT UINT32 Device:5; ///< Device number
IN OUT UINT32 Bus:8; ///< Bus number
IN OUT UINT32 Segment:4; ///< Segment
} EXT_PCI_ADDR;
/// Union type for PCI address
typedef union _PCI_ADDR {
IN UINT32 AddressValue; ///< Formal address
IN EXT_PCI_ADDR Address; ///< Extended address
} PCI_ADDR;
// SBDFO - Segment Bus Device Function Offset
// 31:28 Segment (4-bits)
// 27:20 Bus (8-bits)
// 19:15 Device (5-bits)
// 14:12 Function(3-bits)
// 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
#define ILLEGAL_SBDFO 0xFFFFFFFFul
/// CPUID data received registers format
typedef struct {
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
} CPUID_DATA;
// Topology Services definitions and macros
#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
#ifndef BIT0
#define BIT0 0x0000000000000001ull
#endif
#ifndef BIT1
#define BIT1 0x0000000000000002ull
#endif
#ifndef BIT2
#define BIT2 0x0000000000000004ull
#endif
#ifndef BIT3
#define BIT3 0x0000000000000008ull
#endif
#ifndef BIT4
#define BIT4 0x0000000000000010ull
#endif
#ifndef BIT5
#define BIT5 0x0000000000000020ull
#endif
#ifndef BIT6
#define BIT6 0x0000000000000040ull
#endif
#ifndef BIT7
#define BIT7 0x0000000000000080ull
#endif
#ifndef BIT8
#define BIT8 0x0000000000000100ull
#endif
#ifndef BIT9
#define BIT9 0x0000000000000200ull
#endif
#ifndef BIT10
#define BIT10 0x0000000000000400ull
#endif
#ifndef BIT11
#define BIT11 0x0000000000000800ull
#endif
#ifndef BIT12
#define BIT12 0x0000000000001000ull
#endif
#ifndef BIT13
#define BIT13 0x0000000000002000ull
#endif
#ifndef BIT14
#define BIT14 0x0000000000004000ull
#endif
#ifndef BIT15
#define BIT15 0x0000000000008000ull
#endif
#ifndef BIT16
#define BIT16 0x0000000000010000ull
#endif
#ifndef BIT17
#define BIT17 0x0000000000020000ull
#endif
#ifndef BIT18
#define BIT18 0x0000000000040000ull
#endif
#ifndef BIT19
#define BIT19 0x0000000000080000ull
#endif
#ifndef BIT20
#define BIT20 0x0000000000100000ull
#endif
#ifndef BIT21
#define BIT21 0x0000000000200000ull
#endif
#ifndef BIT22
#define BIT22 0x0000000000400000ull
#endif
#ifndef BIT23
#define BIT23 0x0000000000800000ull
#endif
#ifndef BIT24
#define BIT24 0x0000000001000000ull
#endif
#ifndef BIT25
#define BIT25 0x0000000002000000ull
#endif
#ifndef BIT26
#define BIT26 0x0000000004000000ull
#endif
#ifndef BIT27
#define BIT27 0x0000000008000000ull
#endif
#ifndef BIT28
#define BIT28 0x0000000010000000ull
#endif
#ifndef BIT29
#define BIT29 0x0000000020000000ull
#endif
#ifndef BIT30
#define BIT30 0x0000000040000000ull
#endif
#ifndef BIT31
#define BIT31 0x0000000080000000ull
#endif
#ifndef BIT32
#define BIT32 0x0000000100000000ull
#endif
#ifndef BIT33
#define BIT33 0x0000000200000000ull
#endif
#ifndef BIT34
#define BIT34 0x0000000400000000ull
#endif
#ifndef BIT35
#define BIT35 0x0000000800000000ull
#endif
#ifndef BIT36
#define BIT36 0x0000001000000000ull
#endif
#ifndef BIT37
#define BIT37 0x0000002000000000ull
#endif
#ifndef BIT38
#define BIT38 0x0000004000000000ull
#endif
#ifndef BIT39
#define BIT39 0x0000008000000000ull
#endif
#ifndef BIT40
#define BIT40 0x0000010000000000ull
#endif
#ifndef BIT41
#define BIT41 0x0000020000000000ull
#endif
#ifndef BIT42
#define BIT42 0x0000040000000000ull
#endif
#ifndef BIT43
#define BIT43 0x0000080000000000ull
#endif
#ifndef BIT44
#define BIT44 0x0000100000000000ull
#endif
#ifndef BIT45
#define BIT45 0x0000200000000000ull
#endif
#ifndef BIT46
#define BIT46 0x0000400000000000ull
#endif
#ifndef BIT47
#define BIT47 0x0000800000000000ull
#endif
#ifndef BIT48
#define BIT48 0x0001000000000000ull
#endif
#ifndef BIT49
#define BIT49 0x0002000000000000ull
#endif
#ifndef BIT50
#define BIT50 0x0004000000000000ull
#endif
#ifndef BIT51
#define BIT51 0x0008000000000000ull
#endif
#ifndef BIT52
#define BIT52 0x0010000000000000ull
#endif
#ifndef BIT53
#define BIT53 0x0020000000000000ull
#endif
#ifndef BIT54
#define BIT54 0x0040000000000000ull
#endif
#ifndef BIT55
#define BIT55 0x0080000000000000ull
#endif
#ifndef BIT56
#define BIT56 0x0100000000000000ull
#endif
#ifndef BIT57
#define BIT57 0x0200000000000000ull
#endif
#ifndef BIT58
#define BIT58 0x0400000000000000ull
#endif
#ifndef BIT59
#define BIT59 0x0800000000000000ull
#endif
#ifndef BIT60
#define BIT60 0x1000000000000000ull
#endif
#ifndef BIT61
#define BIT61 0x2000000000000000ull
#endif
#ifndef BIT62
#define BIT62 0x4000000000000000ull
#endif
#ifndef BIT63
#define BIT63 0x8000000000000000ull
#endif
#endif // _AMD_H_

51
src/vendorcode/amd/pi/00630F01/Dispatcher.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Pushhigh Interface
*
* Contains interface to Pushhigh entry
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
#ifndef _DISPATCHER_H_
#define _DISPATCHER_H_
// AGESA function prototypes
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
#endif // _DISPATCHER_H_

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src/vendorcode/amd/pi/00630F01/Include/Filecode.h
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/* $NoKeywords:$ */
/**
* @file
*
* Collectively assign unique filecodes for assert and debug to each source file.
*
* Publish values for decorated filenames, which can be used for
* ASSERT and debug support using a preprocessor define like:
* @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
* This file serves as a reference for debugging to associate the code and filename.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 284995 $ @e \$Date: 2014-02-17 11:17:41 -0600 (Mon, 17 Feb 2014) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _FILECODE_H_
#define _FILECODE_H_
#define UNASSIGNED_FILE_FILECODE (0xFFFF)
/// For debug use in any Platform's options C file.
/// Can be reused for platforms and image builds, since only one options file can be built.
#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033)
#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034)
#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A)
#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B)
#define PROC_GNB_MODULES_GNBPCIECOMMCLKCFG_PCIECOMMCLKCFG_FILECODE (0xA04C)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091)
#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE (0xA092)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093)
#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE (0xA094)
#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE (0xA095)
#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE (0xA096)
#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE (0xA097)
#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE (0xA098)
#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE (0xA09A)
#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE (0xA09B)
#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE (0xA09C)
#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE (0xA09D)
#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE (0xA09E)
#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE (0xA09F)
#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE (0xA0A0)
#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE (0xA0A1)
#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE (0xA0A2)
#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE (0xA0A3)
#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE (0xA0A4)
#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE (0xA0A5)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6)
#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7)
#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8)
#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9)
#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA)
#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE (0xA0AB)
#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE (0xA0B8)
#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE (0xA0B9)
#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA)
#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB)
#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE (0xA0BD)
#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF)
#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0)
#define PROC_GNB_MODULES_GNBINITTN_GNBBAPMCOEFFCALCTN_FILECODE (0xA0C1)
#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE (0xA0C2)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEASPMEXITLATENCYV5_FILECODE (0xA0C5)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB)
#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD)
#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE (0xA0DF)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0)
#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE)
#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE (0xA0F4)
#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100)
#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101)
#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102)
#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
#define PROC_GNB_GNBINITATS3SAVE_FILECODE (0xAE03)
#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04)
#define PROC_GNB_MODULES_GNBINITKV_GFXENVINITKV_FILECODE (0xAE05)
#define PROC_GNB_MODULES_GNBINITKV_GFXINTEGRATEDINFOTABLEKV_FILECODE (0xAE06)
#define PROC_GNB_MODULES_GNBINITKV_GFXMIDINITKV_FILECODE (0xAE07)
#define PROC_GNB_MODULES_GNBINITKV_GFXPOSTINITKV_FILECODE (0xAE08)
#define PROC_GNB_MODULES_GNBINITKV_GNBEARLYINITKV_FILECODE (0xAE09)
#define PROC_GNB_MODULES_GNBINITKV_GNBENVINITKV_FILECODE (0xAE0A)
#define PROC_GNB_MODULES_GNBINITKV_GNBIOMMUIVRSKV_FILECODE (0xAE0B)
#define PROC_GNB_MODULES_GNBINITKV_GNBMIDINITKV_FILECODE (0xAE0C)
#define PROC_GNB_MODULES_GNBINITKV_GNBPOSTINITKV_FILECODE (0xAE0D)
#define PROC_GNB_MODULES_GNBINITKV_GNBREGISTERACCKV_FILECODE (0xAE0E)
#define PROC_GNB_MODULES_GNBINITKV_PCIECOMPLEXDATAKV_FILECODE (0xAE0F)
#define PROC_GNB_MODULES_GNBINITKV_PCIECONFIGKV_FILECODE (0xAE10)
#define PROC_GNB_MODULES_GNBINITKV_PCIEEARLYINITKV_FILECODE (0xAE11)
#define PROC_GNB_MODULES_GNBINITKV_PCIEENVINITKV_FILECODE (0xAE12)
#define PROC_GNB_MODULES_GNBINITKV_PCIELIBKV_FILECODE (0xAE13)
#define PROC_GNB_MODULES_GNBINITKV_PCIEMIDINITKV_FILECODE (0xAE14)
#define PROC_GNB_MODULES_GNBINITKV_PCIEPOSTINITKV_FILECODE (0xAE15)
#define PROC_GNB_MODULES_GNBINITKV_GFXLIBKV_FILECODE (0xAE16)
#define PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE (0xAE18)
#define PROC_GNB_MODULES_GNBINITKV_GFXGMCINITKV_FILECODE (0xAE19)
#define PROC_GNB_MODULES_GNBSMULIBV7_GNBSMUINITLIBV7_FILECODE (0xAE1A)
#define PROC_GNB_MODULES_GNBINITKV_GNBSMUBIOSTABLEKV_FILECODE (0xAE1B)
#define PROC_GNB_MODULES_GNBINITKV_PCIEPOWERGATEKV_FILECODE (0xAE1C)
#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE (0xAE33)
#define PROC_GNB_MODULES_GNBINITKV_ALIBKVD_FILECODE (0xAE34)
#define PROC_GNB_MODULES_GNBINITKV_ALIBKVM_FILECODE (0xAE35)
#define PROC_GNB_MODULES_GNBINITKV_GNBFUSETABLEKV_FILECODE (0xAE39)
#define PROC_GNB_MODULES_GNBURALIBV1_GNBURALIBV1_FILECODE (0xAE3A)
#define PROC_GNB_MODULES_GNBINITKV_GNBURAKV_FILECODE (0xAE3B)
#define PROC_GNB_MODULES_GNBINITKV_GNBURATOKENMAPKV_FILECODE (0xAE3C)
#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXLIBV3_FILECODE (0xAE41)
#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXINTEGRATEDINFOTABLE_FILECODE (0xAE42)
#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXPWRPLAYTABLE_FILECODE (0xAE43)
#define PROC_GNB_MODULES_GNBSCSLIBV1_GNBSCSLIBV1_FILECODE (0xAE44)
// FCH
#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB001)
#define PROC_FCH_AZALIA_AZALIAENV_FILECODE (0xB002)
#define PROC_FCH_AZALIA_AZALIAMID_FILECODE (0xB003)
#define PROC_FCH_AZALIA_AZALIALATE_FILECODE (0xB004)
#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011)
#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016)
#define PROC_FCH_GEC_GECRESET_FILECODE (0xB020)
#define PROC_FCH_GEC_GECENV_FILECODE (0xB021)
#define PROC_FCH_GEC_GECMID_FILECODE (0xB022)
#define PROC_FCH_GEC_GECLATE_FILECODE (0xB023)
#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE (0xB024)
#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE (0xB025)
#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE (0xB030)
#define PROC_FCH_HWACPI_HWACPIENV_FILECODE (0xB031)
#define PROC_FCH_HWACPI_HWACPIMID_FILECODE (0xB032)
#define PROC_FCH_HWACPI_HWACPILATE_FILECODE (0xB033)
#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE (0xB034)
#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE (0xB035)
#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036)
#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE (0xB037)
#define PROC_FCH_HWM_HWMRESET_FILECODE (0xB050)
#define PROC_FCH_HWM_HWMENV_FILECODE (0xB051)
#define PROC_FCH_HWM_HWMMID_FILECODE (0xB052)
#define PROC_FCH_HWM_HWMLATE_FILECODE (0xB053)
#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE (0xB054)
#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE (0xB055)
#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE (0xB056)
#define PROC_FCH_IMC_IMCENV_FILECODE (0xB060)
#define PROC_FCH_IMC_IMCMID_FILECODE (0xB061)
#define PROC_FCH_IMC_IMCLATE_FILECODE (0xB062)
#define PROC_FCH_IMC_IMCLIB_FILECODE (0xB063)
#define PROC_FCH_IMC_IMCRESET_FILECODE (0xB064)
#define PROC_FCH_IMC_FCHECENV_FILECODE (0xB065)
#define PROC_FCH_IMC_FCHECMID_FILECODE (0xB066)
#define PROC_FCH_IMC_FCHECLATE_FILECODE (0xB067)
#define PROC_FCH_IMC_FCHECRESET_FILECODE (0xB068)
#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE (0xB069)
#define PROC_FCH_IDE_IDEENV_FILECODE (0xB06D)
#define PROC_FCH_IDE_IDEMID_FILECODE (0xB06E)
#define PROC_FCH_IDE_IDELATE_FILECODE (0xB06F)
#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB070)
#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB071)
#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB072)
#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB073)
#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB074)
#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB075)
#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB076)
#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB077)
#define PROC_FCH_IR_IRENV_FILECODE (0xB080)
#define PROC_FCH_IR_IRMID_FILECODE (0xB081)
#define PROC_FCH_IR_IRLATE_FILECODE (0xB082)
#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB090)
#define PROC_FCH_PCIB_PCIBENV_FILECODE (0xB091)
#define PROC_FCH_PCIB_PCIBMID_FILECODE (0xB092)
#define PROC_FCH_PCIB_PCIBLATE_FILECODE (0xB093)
#define PROC_FCH_PCIE_ABRESET_FILECODE (0xB0A0)
#define PROC_FCH_PCIE_ABENV_FILECODE (0xB0A1)
#define PROC_FCH_PCIE_ABMID_FILECODE (0xB0A2)
#define PROC_FCH_PCIE_ABLATE_FILECODE (0xB0A3)
#define PROC_FCH_PCIE_GPPHP_FILECODE (0xB0A4)
#define PROC_FCH_PCIE_GPPLIB_FILECODE (0xB0A5)
#define PROC_FCH_PCIE_GPPRESET_FILECODE (0xB0A6)
#define PROC_FCH_PCIE_GPPENV_FILECODE (0xB0A7)
#define PROC_FCH_PCIE_GPPMID_FILECODE (0xB0A8)
#define PROC_FCH_PCIE_GPPLATE_FILECODE (0xB0A9)
#define PROC_FCH_PCIE_PCIERESET_FILECODE (0xB0AA)
#define PROC_FCH_PCIE_PCIEENV_FILECODE (0xB0AB)
#define PROC_FCH_PCIE_PCIEMID_FILECODE (0xB0AC)
#define PROC_FCH_PCIE_PCIELATE_FILECODE (0xB0AD)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE (0xB0AE)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE (0xB0AF)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE (0xB0B0)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE (0xB0B1)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE (0xB0B2)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE (0xB0B3)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE (0xB0B4)
#define PROC_FCH_SATA_AHCIENV_FILECODE (0xB0C0)
#define PROC_FCH_SATA_AHCIMID_FILECODE (0xB0C1)
#define PROC_FCH_SATA_AHCILATE_FILECODE (0xB0C2)
#define PROC_FCH_SATA_AHCILIB_FILECODE (0xB0C3)
#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE (0xB0C4)
#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE (0xB0C5)
#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE (0xB0C6)
#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE (0xB0C7)
#define PROC_FCH_SATA_RAIDENV_FILECODE (0xB0C8)
#define PROC_FCH_SATA_RAIDMID_FILECODE (0xB0C9)
#define PROC_FCH_SATA_RAIDLATE_FILECODE (0xB0CA)
#define PROC_FCH_SATA_RAIDLIB_FILECODE (0xB0CB)
#define PROC_FCH_SATA_SATAENV_FILECODE (0xB0CC)
#define PROC_FCH_SATA_SATAENVLIB_FILECODE (0xB0CD)
#define PROC_FCH_SATA_SATAIDEENV_FILECODE (0xB0CE)
#define PROC_FCH_SATA_SATAIDEMID_FILECODE (0xB0CF)
#define PROC_FCH_SATA_SATAIDELATE_FILECODE (0xB0D0)
#define PROC_FCH_SATA_SATAIDELIB_FILECODE (0xB0D1)
#define PROC_FCH_SATA_SATAMID_FILECODE (0xB0D2)
#define PROC_FCH_SATA_SATALATE_FILECODE (0xB0D3)
#define PROC_FCH_SATA_SATALIB_FILECODE (0xB0D4)
#define PROC_FCH_SATA_SATARESET_FILECODE (0xB0D5)
#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE (0xB0D6)
#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE (0xB0D7)
#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE (0xB0D8)
#define PROC_FCH_SD_SDENV_FILECODE (0xB0E0)
#define PROC_FCH_SD_SDMID_FILECODE (0xB0E1)
#define PROC_FCH_SD_SDLATE_FILECODE (0xB0E2)
#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE (0xB0E3)
#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE (0xB0E4)
#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE (0xB0E5)
#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0F0)
#define PROC_FCH_SPI_LPCENV_FILECODE (0xB0F1)
#define PROC_FCH_SPI_LPCMID_FILECODE (0xB0F2)
#define PROC_FCH_SPI_LPCLATE_FILECODE (0xB0F3)
#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0F4)
#define PROC_FCH_SPI_SPIENV_FILECODE (0xB0F5)
#define PROC_FCH_SPI_SPIMID_FILECODE (0xB0F6)
#define PROC_FCH_SPI_SPILATE_FILECODE (0xB0F7)
#define PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCENVSERVICE_FILECODE (0xB0F8)
#define PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCRESETSERVICE_FILECODE (0xB0F9)
#define PROC_FCH_USB_EHCIRESET_FILECODE (0xB100)
#define PROC_FCH_USB_EHCIENV_FILECODE (0xB101)
#define PROC_FCH_USB_EHCIMID_FILECODE (0xB102)
#define PROC_FCH_USB_EHCILATE_FILECODE (0xB103)
#define PROC_FCH_USB_OHCIRESET_FILECODE (0xB104)
#define PROC_FCH_USB_OHCIENV_FILECODE (0xB105)
#define PROC_FCH_USB_OHCIMID_FILECODE (0xB106)
#define PROC_FCH_USB_OHCILATE_FILECODE (0xB107)
#define PROC_FCH_USB_USBRESET_FILECODE (0xB108)
#define PROC_FCH_USB_USBENV_FILECODE (0xB109)
#define PROC_FCH_USB_USBMID_FILECODE (0xB10A)
#define PROC_FCH_USB_USBLATE_FILECODE (0xB10B)
#define PROC_FCH_USB_XHCIRESET_FILECODE (0xB10C)
#define PROC_FCH_USB_XHCIENV_FILECODE (0xB10D)
#define PROC_FCH_USB_XHCIMID_FILECODE (0xB10E)
#define PROC_FCH_USB_XHCILATE_FILECODE (0xB10F)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE (0xB110)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE (0xB111)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE (0xB112)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE (0xB113)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE (0xB114)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE (0xB115)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE (0xB116)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE (0xB117)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE (0xB118)
#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE (0xB119)
#define PROC_FCH_USB_XHCIRECOVERY_FILECODE (0xB12E)
#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE (0xB12F)
#define PROC_FCH_SPI_FAMILY_YUBA_YUBALPCRESETSERVICE_FILECODE (0xB160)
#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE (0xB200)
#define UEFI_DXE_FCHDXE_USBOC_FILECODE (0xB201)
#define UEFI_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB202)
#define UEFI_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB203)
#define UEFI_DXE_FCHDXELPCCLKRUN_FCHDXELPCCLKRUN_FILECODE (0xB204)
#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB210)
#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB211)
#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB212)
#define UEFI_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB213)
#define UEFI_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB214)
#define UEFI_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB215)
#define UEFI_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB216)
#define UEFI_DXE_AMDIGPUVGACONTROLDXE_AMDIGPUVGACONTROLDXE_FILECODE (0xB218)
#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220)
#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221)
#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222)
#define UEFI_DXE_FCHDXEMMIO_FCHDXEMMIO_FILECODE (0xB223)
#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230)
#define UEFI_DXE_FCHACPICS_FCHACPICS_FILECODE (0xB231)
#define UEFI_DXE_FCHACPICS_FCHACPICSAML_FILECODE (0xB232)
#define UEFI_DXE_FCHACPICS_FCHACPICSCONTROL_FILECODE (0xB233)
#define UEFI_DXE_FCHACPICS_FUNCTIONS_POWERBUTTON_POWERBUTTON_FILECODE (0xB234)
#define UEFI_DXE_FCHACPICS_FUNCTIONS_SMBUSNFC_SMBUSNFC_FILECODE (0xB235)
#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240)
#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250)
#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251)
#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB252)
#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE (0xB260)
#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE (0xB261)
#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE (0xB262)
#define UEFI_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB263)
#define UEFI_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB264)
#define UEFI_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB265)
#define UEFI_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB266)
#define UEFI_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB267)
#define UEFI_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB268)
#define UEFI_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB269)
#define UEFI_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB26A)
#define UEFI_PEI_FCHPEIAUX_PEIOSCOUTCLOCK_FILECODE (0xB26B)
#define UEFI_PEI_FCHPEI_FCHEHCIRECOVERY_FILECODE (0xB280)
#define UEFI_PEI_FCHPEI_FCHSATARECOVERY_FILECODE (0xB281)
#define UEFI_PEI_FCHPEI_FCHXHCIRECOVERY_FILECODE (0xB282)
#define UEFI_PEI_FCHPEI_FCHGPPRECOVERY_FILECODE (0xB283)
#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB28A)
#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE (0xB290)
#define UEFI_SMM_FCHSMMCOMPLEMENT_SDIOPOWER_SDIOPOWER_FILECODE (0xB291)
#define UEFI_SMM_FCHSMMCOMPLEMENT_USB3PORTPROTECTWA_USB3PORTPROTECTWA_FILECODE (0xB292)
#define UEFI_SMM_FCHSMM_GPESMI_FILECODE (0xB293)
#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB294)
#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE (0xB295)
#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB296)
#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB297)
#define UEFI_SMM_FCHSMM_SWSMI_FILECODE (0xB298)
#define UEFI_SMM_FCHSMM_SXSMI_FILECODE (0xB299)
#define UEFI_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROL_FILECODE (0xB29A)
#define UEFI_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROLLIB_FILECODE (0xB29B)
#define UEFI_SMM_FCHSMMCOMPLEMENT_USB3PORTPROTECTWA_LIBAMDSMMLIB_FILECODE (0xB29C)
#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHPCIEWAKEWA_FCHPCIEWAKEWA_FILECODE (0xB29D)
#define UEFI_SMM_FCHSMMCOMPLEMENT_SDCLKDRIVINGLOWWA_SDCLKDRIVINGLOWWA_FILECODE (0xB29E)
#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHSDVOLTAGESWITCH_FCHSDVOLTAGESWITCH_FILECODE (0xB29F)
#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0)
#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHIMCSPIWA_FCHIMCSPIWA_FILECODE (0xB2A1)
#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHXHCD3WA_FCHXHCD3WA_FILECODE (0xB2A2)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB2B0)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB2B1)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB2B2)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB2B3)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB2B4)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB2B5)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB2B6)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB2B7)
#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB2B8)
#define PROC_FCH_PCIE_GPPALLINONE_FILECODE (0xB2C0)
#define UEFI_SMM_MEMSMMLIB_MEMSMMLIB_FILECODE (0xB2C1)
#define UEFI_SMM_MEMSMMLIB_KV_DRAMMAPKV_FILECODE (0xB2C3)
#define LIB_AMDLIB_FILECODE (0xC001)
#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
#define UEFI_PROC_COMMON_HOBTRANSFERUEFI_FILECODE (0xC160)
#define UEFI_PROC_DXE_HOBTRANSFERUEFIDXE_FILECODE (0xC161)
#define UEFI_PROC_PEI_HOBTRANSFERUEFIPEI_FILECODE (0xC162)
#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
#define PROC_COMMON_AMDS3FINALRESTORE_FILECODE (0xC02B)
#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
#define PROC_CPU_TABLE_FILECODE (0xC403)
#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F)
#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431)
#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
#define PROC_CPU_S3_FILECODE (0xC460)
// Family 15h
#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02)
#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03)
#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04)
#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB05)
#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB06)
#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB07)
#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08)
#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09)
#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE (0xCB0A)
#define PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE (0xCB0B)
#define PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE (0xCB0C)
#define PROC_CPU_FAMILY_0X15_CPUF15PREFETCHMODE_FILECODE (0xCB0D)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE (0xCB50)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE (0xCB51)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE (0xCB52)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE (0xCB53)
#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE (0xCB54)
#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE (0xCB55)
#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE (0xCB56)
#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE (0xCB57)
#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE (0xCB58)
#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE (0xCB59)
#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE (0xCB5A)
#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE (0xCB5B)
#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE (0xCB5C)
#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE (0xCB5D)
#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE (0xCB5E)
#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE (0xCB5F)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE (0xCB60)
#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE (0xCB62)
#define PROC_CPU_FAMILY_0X15_TN_F15TNEARLYSAMPLES_FILECODE (0xCB63)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPOWERCHECK_FILECODE (0xCB64)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSI_FILECODE (0xCB65)
#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNHTC_FILECODE (0xCB66)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCOREAFTERRESET_FILECODE (0xCBE0)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVDMI_FILECODE (0xCBE1)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVNBAFTERRESET_FILECODE (0xCBE2)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPSTATE_FILECODE (0xCBE3)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVLOGICALIDTABLES_FILECODE (0xCBE4)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVMICROCODEPATCHTABLES_FILECODE (0xCBE5)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVMSRTABLES_FILECODE (0xCBE6)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVSHAREDMSRTABLE_FILECODE (0xCBE7)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVEQUIVALENCETABLE_FILECODE (0xCBE8)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPCITABLES_FILECODE (0xCBE9)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPOWERMGMTSYSTEMTABLES_FILECODE (0xCBEA)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVBRANDID_FILECODE (0xCBEB)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVUTILITIES_FILECODE (0xCBEC)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVC6STATE_FILECODE (0xCBED)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCPB_FILECODE (0xCBEE)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVIOCSTATE_FILECODE (0xCBEF)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCACHEFLUSHONHALT_FILECODE (0xCBF0)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVHTC_FILECODE (0xCBF1)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVINITEARLYTABLE_FILECODE (0xCBF2)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVEARLYSAMPLES_FILECODE (0xCBF3)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPOWERCHECK_FILECODE (0xCBF4)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPSI_FILECODE (0xCBF5)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVSCS_FILECODE (0xCBF6)
#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCC6EXITCONTROL_FILECODE (0xCBF7)
#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84)
#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC86)
#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC0)
#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC1)
#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0)
#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1)
#define PROC_CPU_FEATURE_CPUPREFETCHMODE_FILECODE (0xDCD3)
#define PROC_CPU_FEATURE_CPUSCS_FILECODE (0xDCD4)
#define PROC_CPU_FEATURE_CPUCC6EXITCONTROL_FILECODE (0xDCD5)
#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
#define PROC_TOPOLOGY_TOPOMAIN_FILECODE (0xE001)
#define PROC_TOPOLOGY_TOPONB_FILECODE (0xE002)
#define PROC_TOPOLOGY_FAM15_TOPONBFAM15_FILECODE (0xE087)
#define PROC_TOPOLOGY_FAM15_TOPONBUTILITIESFAM15_FILECODE (0xE088)
#define PROC_TOPOLOGY_FAM16_TOPONBFAM16_FILECODE (0xE097)
#define PROC_TOPOLOGY_FAM16_TOPONBUTILITIESFAM16_FILECODE (0xE098)
#define PROC_RECOVERY_TOPOLOGY_TOPOINITRECOVERY_FILECODE (0xE0FF)
#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802)
#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C)
#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE (0xE80F)
#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810)
#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811)
#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812)
#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813)
#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814)
#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE (0xE815)
#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E)
#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F)
#define PROC_IDS_FAMILY_0X15_KV_IDSF15KVALLSERVICE_FILECODE (0xE820)
///0xE820 ~ 0xE840 is reserved for ids extend module
#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
#define PROC_MEM_FEAT_CHINTLV_MFMCHI_FILECODE (0xF094)
#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE (0xF095)
#define PROC_MEM_FEAT_AMP_MFAMP_FILECODE (0xF096)
#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE (0xF097)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE (0xF098)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE (0xF099)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE (0xF09A)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE (0xF09B)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C)
#define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F)
#define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0)
#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119)
#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C)
#define PROC_MEM_MAIN_KV_MMFLOWD3KV_FILECODE (0xF122)
#define PROC_MEM_NB_MN_FILECODE (0xF27C)
#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D)
#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E)
#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F)
#define PROC_MEM_NB_MNS3_FILECODE (0xF280)
#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281)
#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282)
#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284)
#define PROC_MEM_NB_MNREG_FILECODE (0xF285)
#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0xF29B)
#define PROC_MEM_NB_TN_MNTN_FILECODE (0xF29C)
#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0xF29D)
#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0xF29E)
#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0xF29F)
#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0xF2A0)
#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0xF2A1)
#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0xF2A2)
#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0xF2A3)
#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0xF2A4)
#define PROC_MEM_NB_KV_MNKV_FILECODE (0xF2AF)
#define PROC_MEM_NB_KV_MNMCTKV_FILECODE (0xF2B0)
#define PROC_MEM_NB_KV_MNDCTKV_FILECODE (0xF2B1)
#define PROC_MEM_NB_KV_MNPHYKV_FILECODE (0xF2B2)
#define PROC_MEM_NB_KV_MNS3KV_FILECODE (0xF2B3)
#define PROC_MEM_NB_KV_MNIDENDIMMKV_FILECODE (0xF2B4)
#define PROC_MEM_NB_KV_MNPROTOKV_FILECODE (0xF2B5)
#define PROC_MEM_NB_KV_MNREGKV_FILECODE (0xF2B6)
#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7)
#define PROC_MEM_NB_KV_MNPMUKV_FILECODE (0xF2C2)
#define PROC_MEM_NB_KV_MNPMUSRAMMSGBLOCKKV_FILECODE (0xF2D7)
#define PROC_MEM_PS_MP_FILECODE (0xF401)
#define PROC_MEM_PS_MPRTT_FILECODE (0xF422)
#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423)
#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424)
#define PROC_MEM_PS_MPSAO_FILECODE (0xF425)
#define PROC_MEM_PS_MPMR0_FILECODE (0xF426)
#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427)
#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428)
#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429)
#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A)
#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B)
#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0xF42D)
#define PROC_MEM_PS_TN_MPTN3_FILECODE (0xF42E)
#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0xF42F)
#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0xF430)
#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0xF431)
#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0xF432)
#define PROC_MEM_PS_MPS2D_FILECODE (0xF436)
#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437)
#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C)
#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D)
#define PROC_MEM_PS_KV_MPKV3_FILECODE (0xF43E)
#define PROC_MEM_PS_KV_MPSKV3_FILECODE (0xF43F)
#define PROC_MEM_PS_KV_MPUKV3_FILECODE (0xF440)
#define PROC_MEM_TECH_MT_FILECODE (0xF501)
#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502)
#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504)
#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505)
#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506)
#define PROC_MEM_TECH_MTTML_FILECODE (0xF507)
#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509)
#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B)
#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C)
#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581)
#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583)
#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584)
#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585)
#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586)
#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587)
#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588)
#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589)
#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A)
#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B)
#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C)
#define PROC_MEM_TECH_GDDR5_MNSPDG5_FILECODE (0xF58E)
#define PROC_MEM_TECH_GDDR5_MNDCTG5_FILECODE (0xF58F)
#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801)
#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802)
#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803)
#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804)
#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1)
#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7)
#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8)
#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9)
#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA)
#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB)
#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC)
#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0)
#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1)
#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2)
#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3)
#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4)
#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5)
#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6)
#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7)
#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8)
#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9)
#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0xF8F3)
#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0xF8F4)
#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0xF8F5)
#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0xF8F6)
#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0xF8F7)
#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0xF8F8)
#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0xF8F9)
#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA)
//Psp
#define UEFI_PSP_DRIVERS_ITPMDXE_ITPMDXE_FILECODE (0xFA00)
#define UEFI_PSP_DRIVERS_ITPMPEI_ITPMPEI_FILECODE (0xFA01)
#define UEFI_PSP_DRIVERS_ITPMSMM_ITPMPSPCOMMAND_FILECODE (0xFA02)
#define UEFI_PSP_DRIVERS_ITPMSMM_ITPMSMM_FILECODE (0xFA03)
#define UEFI_PSP_DRIVERS_PSPPEI_PSPPEI_FILECODE (0xFA04)
#define UEFI_PSP_DRIVERS_PSPSMM_PSPRESUMEHANDLING_FILECODE (0xFA05)
#define UEFI_PSP_DRIVERS_PSPSMM_PSPRESUMESERVICES_FILECODE (0xFA06)
#define UEFI_PSP_DRIVERS_PSPSMM_PSPSMM_FILECODE (0xFA07)
#define UEFI_PSP_LIBRARY_PSPBASELIB_PSPBASELIB_FILECODE (0xFA08)
#define UEFI_PSP_LIBRARY_PSPMBOX_PSPMBOX_FILECODE (0xFA09)
#define UEFI_PSP_LIBRARY_SMMLOAD_SMMLOAD_FILECODE (0xFA0A)
#define UEFI_PSP_DRIVERS_PSPDXE_PSPDXE_FILECODE (0xFA0B)
#define UEFI_PSP_LIBRARY_PSPFTPMLIB_PSPFTPMLIB_FILECODE (0xFA0C)
#define UEFI_PSP_LIBRARY_CCPSHALIB_CCPSHALIB_FILECODE (0xFA0D)
#endif // _FILECODE_H_

1428
src/vendorcode/amd/pi/00630F01/Include/Ids.h
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src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Integrated Debug Routines for performance analysis
*
* Contains AMD AGESA debug macros and functions for performance analysis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_PERFORMANCE_DATA_POINT
#define _IDS_PERFORMANCE_DATA_POINT
#define IDS_PERF_VERSION 0x00010000ul //version number 0.1.0.0
/// Time points performance function used
typedef enum {
TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly
TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly
TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize
TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize
TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier
TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier
TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly
TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly
TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly
TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly
TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv
TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv
TP_BEGININITENV = 0x10C, ///< BeginInitEnv
TP_ENDINITENV = 0x10D, ///< EndInitEnv
TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv
TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv
TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate
TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate
TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable
TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable
TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate
TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate
TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate
TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate
TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate
TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate
TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid
TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid
TP_BEGININITMID = 0x11E, ///< BeginInitMid
TP_ENDINITMID = 0x11F, ///< EndInitMid
TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid
TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid
TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost
TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost
TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost
TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost
TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto
TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto
TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost
TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost
TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram
TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram
TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset
TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset
TP_BEGININITRESET = 0x12E, ///< BeginInitReset
TP_ENDINITRESET = 0x12F, ///< EndInitReset
TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset
TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset
TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume
TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume
TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume
TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume
TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume
TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume
TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel
TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel
TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init
TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init
TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit
TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit
TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto
TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto
TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32
TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32
TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT
TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT
TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping
TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping
TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining
TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining
TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming
TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming
TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping
TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping
TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr
TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr
TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN
TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN
TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit
TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit
TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining
TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining
TP_BEGINGNBINITATS3SAVE = 0x154, ///< BeginGnbInitAtS3Save
TP_ENDGNBINITATS3SAVE = 0x155, ///< EndGnbInitAtS3Save
TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData
TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData
TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining
TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining
IDS_TP_END ///< End of IDS TP list
} IDS_PERF_DATA;
#endif

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src/vendorcode/amd/pi/00630F01/Include/Options.h
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/* $NoKeywords:$ */
/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#endif // _OPTIONS_H_

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src/vendorcode/amd/pi/00630F01/Include/PlatformMemoryConfiguration.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Platform Specific Memory Configuration
*
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*****************************************************************************
*
* Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
#define _PLATFORM_MEMORY_CONFIGURATION_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
#ifndef PSO_ENTRY
#define PSO_ENTRY UINT8
#endif
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* PLATFORM SPECIFIC MEMORY DEFINITIONS
*----------------------------------------------------------------------------------------
*/
///
/// Memory Speed and DIMM Population Masks
///
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
#define ANY_SPEED 0xFFFFFFFFul
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
///
///< DIMM POPULATION MASKS
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
///
#define ANY_ 0xFF ///< Any dimm configuration the current channel
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
///
///< CS POPULATION MASKS
///< Specifies the CS Population on a channel (can be added together to specify configuration).
///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
///
#define CS_ANY_ 0xFF ///< Any CS configuration
#define CS0_ 0x01 ///< CS0 bit map mask
#define CS1_ 0x02 ///< CS1 bit map mask
#define CS2_ 0x04 ///< CS2 bit map mask
#define CS3_ 0x08 ///< CS3 bit map mask
#define CS4_ 0x10 ///< CS4 bit map mask
#define CS5_ 0x20 ///< CS5 bit map mask
#define CS6_ 0x40 ///< CS6 bit map mask
#define CS7_ 0x80 ///< CS7 bit map mask
///
///< Number of Dimms on the current channel
///< This is a mask used to indicate the number of dimms in a channel
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
///
#define ANY_NUM 0xFF ///< Any number of Dimms
#define NO_DIMM 0x00 ///< No Dimms present
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
///
///< DIMM VOLTAGE MASKS
///
#define VOLT_ANY_ 0xFF ///< Any voltage configuration
#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
//
// < Not applicable
//
#define NA_ 0 ///< Not applicable
/*----------------------------------------------------------------------------------------
*
* Platform Specific Override Definitions for Socket, Channel and Dimm
* This indicates where a platform override will be applied.
*
*----------------------------------------------------------------------------------------
*/
///
///< SOCKET MASKS
///< Indicates associated processor sockets to apply override settings
///
#define ANY_SOCKET 0xFF ///< Apply to all sockets
#define SOCKET0 0x01 ///< Apply to socket 0
#define SOCKET1 0x02 ///< Apply to socket 1
#define SOCKET2 0x04 ///< Apply to socket 2
#define SOCKET3 0x08 ///< Apply to socket 3
#define SOCKET4 0x10 ///< Apply to socket 4
#define SOCKET5 0x20 ///< Apply to socket 5
#define SOCKET6 0x40 ///< Apply to socket 6
#define SOCKET7 0x80 ///< Apply to socket 7
///
///< CHANNEL MASKS
///< Indicates Memory channels where override should be applied
///
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
#define CHANNEL_A 0x01 ///< Apply to Channel A
#define CHANNEL_B 0x02 ///< Apply to Channel B
#define CHANNEL_C 0x04 ///< Apply to Channel C
#define CHANNEL_D 0x08 ///< Apply to Channel D
///
/// DIMM MASKS
/// Indicates Dimm Slots where override should be applied
///
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
///
/// REGISTER ACCESS MASKS
/// Not supported as an at this time
///
#define ACCESS_NB0 0x0
#define ACCESS_NB1 0x1
#define ACCESS_NB2 0x2
#define ACCESS_NB3 0x3
#define ACCESS_NB4 0x4
#define ACCESS_PHY 0x5
#define ACCESS_DCT_XT 0x6
///
/// MOTHER BOARD DESIGN LAYERS MASKS
/// Indicates the layer design of mother board
///
#define LAYERS_4 0x0
#define LAYERS_6 0x1
/*----------------------------------------------------------------------------------------
*
* Platform Specific Overriding Table Definitions
*
*----------------------------------------------------------------------------------------
*/
#define PSO_END 0 ///< Table End
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
#define PSO_CS_TRI 3 ///< CS Tristate Map
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
#define PSO_CLK_SPEED 5 ///< Clock Speed
#define PSO_DIMM_TYPE 6 ///< Dimm Type
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
#define PSO_MEM_TECH 11 ///< Channel Memory Type
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
#define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override
#define PSO_MOTHER_BOARD_LAYERS 21 ///< Mother board layer design
/*----------------------------------
* CONDITIONAL PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition Types
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
#define PSO_CONDITION_REG 103 // Reserved
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
// Action Types
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
#define PSO_ACTION_ODT 120 ///< ODT values to override
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
#define PSO_ACTION_REG 124 // Reserved
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
/*----------------------------------
* TABLE DRIVEN PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition descriptor
#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
// Overriding entry types
#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
#define PSO_TBLDRV_2D_TRAINING 222 ///< 2D training
#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
, Bit7Map
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed
#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
#define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \
PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy
#define MOTHER_BOARD_LAYERS(Layers) \
PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CONDITION_AND \
PSO_CONDITION_AND, 0
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
#define COND_SPD(Byte, Mask, Value) \
PSO_CONDITION_SPD, 3, Byte, Mask, Value
#define COND_REG(Access, Offset, Mask, Value) \
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
PSO_ACTION_ODT, 9, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
PSO_ACTION_ADDRTMG, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
PSO_ACTION_ODCCONTROL, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
PSO_ACTION_SLEWRATE, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
PSO_ACTION_SPEEDLIMIT, 9, \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
/*----------------------------------------------------------------------------------------
* END OF CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* TABLE DRIVEN OVERRIDE MACROS
*----------------------------------------------------------------------------------------
*/
/// Configuration sub-descriptors
typedef enum {
CONFIG_GENERAL, ///< CONFIG_GENERAL
CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
CONFIG_RC2IBT, ///< CONFIG_RC2IBT
CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
} Config_Type;
// ====================
// Configuration Macros
// ====================
#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
PSO_TBLDRV_CONFIG, 9, \
CONFIG_GENERAL, \
DimmPerCH, DimmVolt, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
PSO_TBLDRV_CONFIG, 7, \
CONFIG_SPEEDLIMIT, \
DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
PSO_TBLDRV_CONFIG, 10, \
CONFIG_RC2IBT, \
DimmPerCH, DimmVolt, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
NumOfReg
//==================
// Overriding Macros
//==================
#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
PSO_TBLDRV_SPEEDLIMIT, 6, \
(SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
(SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
(SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
PSO_TBLDRV_ODT_RTTNOM, 2, \
TgtCS, RttNom
#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
PSO_TBLDRV_ODT_RTTWR, 2, \
TgtCS, RttWr
#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
PSO_TBLDRV_ODTPATTERN, 16, \
((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
PSO_TBLDRV_ADDRTMG, 4, \
((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
PSO_TBLDRV_ODCCTRL, 4, \
((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
PSO_TBLDRV_SLOWACCMODE, 1, \
SlowAccMode
#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
PSO_TBLDRV_RC2_IBT, 2, \
TgtDimm, IBT
#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_MR0_CL, 3, \
RegValOfTcl, MR0CL13, MR0CL0
#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_MR0_WR, 2, \
RegValOfTwr, MR0WR
#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_RC10_OPSPEED, 5, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
MR10OPSPEED
#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
PSO_TBLDRV_LRDIMM_IBT, 4, \
F0RC8, F1RC0, F1RC1, F1RC2
#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \
PSO_TBLDRV_2D_TRAINING, 1, \
Training2dMode
//============================
// Macros for removing entries
//============================
#define INVALID_CONFIG_FLAG 0x8000
#define TBLDRV_INVALID_CONFIG \
PSO_TBLDRV_INVALID_TYPE, 0
/*----------------------------------------------------------------------------------------
* END OF TABLE DRIVEN OVERRIDE MACROS
*----------------------------------------------------------------------------------------
*/
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_

86
src/vendorcode/amd/pi/00630F01/Include/Topology.h
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@ -1,86 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Topology interface definitions.
*
* Contains AMD AGESA internal interface for topology related data which
* is consumed by code other than Topology Services init.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _TOPOLOGY_H_
#define _TOPOLOGY_H_
// Defines for limiting data structure maximum allocation and limit checking.
#define MAX_NODES 1
#define MAX_SOCKETS MAX_NODES
#define MAX_DIES 1
/**
* Socket and Module to Node Map Item.
* Provide the Node Id and core id range for each module in each processor.
*/
typedef struct {
UINT8 Node; ///< The module's Node id.
UINT8 LowCore; ///< The lowest processor core id for this module.
UINT8 HighCore; ///< The highest processor core id for this module.
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
UINT8 TripleCoreComputeUnits;///< The value of TripleCore for this processor module.
UINT8 QuadCoreComputeUnits; ///< The value of QuadCore for this processor module.
} SOCKET_DIE_TO_NODE_ITEM;
/**
* Socket and Module to Node Map.
* This type is a pointer to the actual map, it can be used for a struct item or
* for typecasting a heap buffer pointer.
*/
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
/**
* Node id to Socket Die Map Item.
*/
typedef struct {
UINT8 Socket; ///< socket of the processor containing the Node.
UINT8 Die; ///< the module in the processor which is Node.
} NODE_TO_SOCKET_DIE_ITEM;
/**
* Node id to Socket Die Map.
*/
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
#endif // _TOPOLOGY_H_

110
src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h
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@ -1,110 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU Register Table Related Functions
*
* Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_FAM_REGISTERS_H_
#define _CPU_FAM_REGISTERS_H_
/*
*--------------------------------------------------------------
*
* M O D U L E S U S E D
*
*---------------------------------------------------------------
*/
/*
*--------------------------------------------------------------
*
* D E F I N I T I O N S / M A C R O S
*
*---------------------------------------------------------------
*/
// This define should be equal to the total number of families
// in the cpuFamily enum.
#define MAX_CPU_FAMILIES 64
#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family
// CPU_LOGICAL_ID.Family equates
// Family 15h equates
#define AMD_FAMILY_15_TN 0x0000000000000200ull
#define AMD_FAMILY_TN (AMD_FAMILY_15_TN)
#define AMD_FAMILY_15_RL (AMD_FAMILY_15_TN)
#define AMD_FAMILY_RL (AMD_FAMILY_15_TN)
#define AMD_FAMILY_15_KV 0x0000000000000400ull
#define AMD_FAMILY_KV (AMD_FAMILY_15_KV)
#define AMD_FAMILY_15 (AMD_FAMILY_15_TN | AMD_FAMILY_15_KV)
// Family Unknown
#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
// Family 15h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 15h TN steppings
#define AMD_F15_TN_A0 0x0000000000000100ull
#define AMD_F15_TN_A1 0x0000000000000200ull
#define AMD_F15_RL_A1 0x0000000000000400ull
// Family 15h KV steppings
#define AMD_F15_KV_A0 0x0000000000100000ull
#define AMD_F15_KV_A1 0x0000000000200000ull
// Family 15h Unknown stepping
#define AMD_F15_UNKNOWN 0x8000000000000000ull
#define AMD_F15_RL_Ax (AMD_F15_RL_A1)
#define AMD_F15_RL_ALL (AMD_F15_RL_Ax)
#define AMD_F15_TN_Ax (AMD_F15_TN_A0 | AMD_F15_TN_A1)
#define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0)
#define AMD_F15_TN_ONLY (AMD_F15_TN_Ax)
#define AMD_F15_TN_ALL (AMD_F15_TN_Ax | AMD_F15_RL_ALL)
#define AMD_F15_KV_Ax (AMD_F15_KV_A0 | AMD_F15_KV_A1)
#define AMD_F15_KV_ALL (AMD_F15_KV_Ax)
#define AMD_F15_ALL (AMD_F15_TN_ALL | AMD_F15_KV_ALL)
#endif // _CPU_FAM_REGISTERS_H_

138
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/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU Execution Cache Allocation functions.
*
* Contains code for doing Execution Cache Allocation for ROM space
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 192403 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_CACHE_INIT_H_
#define _CPU_CACHE_INIT_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
#define BSP_STACK_SIZE_64K 65536
#define BSP_STACK_SIZE_32K 32768
#define CORE0_STACK_SIZE 16384
#define CORE1_STACK_SIZE 4096
#define AMD_MTRR_FIX4K_BASE 0x268
#define AMD_MTRR_VARIABLE_BASE6 0x20C
#define AMD_MTRR_VARIABLE_BASE7 0x20E
#define WP_IO 0x0505050505050505ull
#define AGESA_CACHE_SIZE_REDUCED 1
#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
#define AGESA_DEALLOCATE_CACHE_REGIONS 7
/*----------------------------------------------------------------------------
* TYPEDEFS, STRUCTURES, ENUMS
*
*----------------------------------------------------------------------------
*/
/// Cache-As-Ram Executable region allocation modes
typedef enum {
LimitedByL2Size, ///< Execution space must be allocated from L2
InfiniteExe, ///< Family can support unlimited Execution space
MaxCarExeMode ///< Used as limit or bounds check
} CAR_EXE_MODE;
/// Cache Information
typedef struct {
IN UINT32 BspStackSize; ///< Stack size of BSP
IN UINT32 Core0StackSize; ///< Stack size of primary cores
IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
IN UINT32 SharedMemSize; ///< Shared memory size
IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
} CACHE_INFO;
/// Merged memory region overlap type
typedef enum {
EmptySet, ///< One of the regions is zero length
Disjoint, ///< The two regions do not touch
Adjacent, ///< one region is next to the other, no gap
CommonEnd, ///< regions overlap with a common end point
Extending, ///< the 2nd region is extending the size of the 1st
Contained, ///< the 2nd region is wholely contained inside the 1st
CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
Identity, ///< the two regions are the same
CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
NotCombinable ///< the combined regions do not follow the cache block rules
} OVERLAP_TYPE;
/// Result of merging two memory regions for cache coverage
typedef struct {
IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
IN OUT UINT32 MergedSize; ///< Size of the merged regions
OUT UINT32 OverlapAmount; ///< the size of the overlapping section
OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
} MERGED_CACHE_REGION;
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
AGESA_STATUS
AllocateExecutionCache (
IN AMD_CONFIG_PARAMS *StdHeader,
IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
);
#endif // _CPU_CACHE_INIT_H_

303
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@ -1,303 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU APIC related utility functions and structures
*
* Contains code that provides mechanism to invoke and control APIC communication.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_APIC_UTILITIES_H_
#define _CPU_APIC_UTILITIES_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
#define APIC_CTRL_DWORD 0xF
#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4)
#define APIC_CTRL_MASK 0xFF
#define APIC_CTRL_SHIFT 0
#define APIC_DATA_DWORD 0x38
#define APIC_DATA_REG (APIC_DATA_DWORD << 4)
#define APIC_REMOTE_READ_REG 0xC0
#define APIC_CMD_LO_REG 0x300
#define APIC_CMD_HI_REG 0x310
// APIC_CMD_LO_REG bits
#define CMD_REG_DELIVERY_STATUS 0x1000
#define CMD_REG_TO_READ 0x300
#define CMD_REG_REMOTE_RD_STS_MSK 0x30000ul
#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000ul
#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000ul
#define CMD_REG_TO_NMI 0x400
// ExeFlags bits
#define WAIT_FOR_CORE 0x00000001ul
#define TASK_HAS_OUTPUT 0x00000002ul
#define RETURN_PARAMS 0x00000004ul
#define END_AT_HLT 0x00000008ul
#define PASS_EARLY_PARAMS 0x00000010ul
// Control Byte Values
// bit 7 indicates the type of message
// 1 - control message
// 0 - launch + APIC ID = message to go
//
#define CORE_UNAVAILABLE 0xFF
#define CORE_IDLE 0xFE
#define CORE_IDLE_HLT 0xFD
#define CORE_ACTIVE 0xFC
#define CORE_NEEDS_PTR 0xFB
#define CORE_NEEDS_DATA_SIZE 0xFA
#define CORE_STS_DATA_READY_1 0xF9
#define CORE_STS_DATA_READY_0 0xF8
#define CORE_DATA_FLAGS_READY 0xF7
#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6
#define CORE_DATA_PTR_READY 0xF5
// Macro used to determine the number of dwords to transmit to the AP as input
#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2))
// IDT table
#define IDT_DESC_PRESENT 0x80
#define IDT_DESC_TYPE_LDT 0x02
#define IDT_DESC_TYPE_CALL16 0x04
#define IDT_DESC_TYPE_TASK 0x05
#define IDT_DESC_TYPE_INT16 0x06
#define IDT_DESC_TYPE_TRAP16 0x07
#define IDT_DESC_TYPE_CALL32 0x0C
#define IDT_DESC_TYPE_INT32 0x0E
#define IDT_DESC_TYPE_TRAP32 0x0F
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader);
typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader);
typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
/// Function pointer union representing the eight different
/// types of functions that an AP can be asked to perform.
typedef union {
PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output
PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output
PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output
PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output
PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
} AP_FUNCTION_PTR;
/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer
/// containing information about the data transfer from one core
/// to another.
typedef struct {
IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword
IN OUT VOID *DataPtr; ///< Pointer to the data
IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer
} AP_DATA_TRANSFER;
/// Input structure for ApUtilRunCodeOnSocketCore.
typedef struct _AP_TASK {
AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run
AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function
UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence
} AP_TASK;
/// Input structure for ApUtilWaitForCoreStatus.
typedef struct {
IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for
IN UINT8 NumberOfElements; ///< Number of elements in the array
IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting
IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus
} AP_WAIT_FOR_STATUS;
/// Interrupt Descriptor Table entry
typedef struct {
UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset
UINT16 Selector; ///< Interrupt handler routine's selector
UINT8 Rsvd; ///< Reserved
UINT8 Flags; ///< Interrupt flags
UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset
UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode
UINT32 Rsvd64; ///< Reserved
} IDT_DESCRIPTOR;
/// Structure needed to load the IDTR using the lidt instruction
typedef struct {
UINT16 Limit; ///< Interrupt Descriptor Table size
UINT64 Base; ///< Interrupt Descriptor Table base address
} IDT_BASE_LIMIT;
#define WAIT_STATUS_EQUALITY 0x00000001ul
#define WAIT_INFINITELY 0
// Data Transfer Flags
#define DATA_IN_MEMORY 0x00000001ul
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
// These are P U B L I C functions, used by AGESA
UINT8
ApUtilReadRemoteControlByte (
IN UINT32 TargetApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
ApUtilWriteControlByte (
IN UINT8 Value,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
ApUtilReadRemoteDataDword (
IN UINT32 TargetApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
ApUtilWriteDataDword (
IN UINT32 Value,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
ApUtilRunCodeOnSocketCore (
IN UINT8 Socket,
IN UINT8 Core,
IN AP_TASK *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
ApUtilWaitForCoreStatus (
IN UINT32 TargetApicId,
IN AP_WAIT_FOR_STATUS *WaitParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
ApEntry (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
);
UINT32
ApUtilTaskOnExecutingCore (
IN AP_TASK *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
);
VOID
ApUtilTransmitBuffer (
IN UINT8 Socket,
IN UINT8 Core,
IN AP_DATA_TRANSFER *BufferInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
ApUtilReceiveBuffer (
IN UINT8 Socket,
IN UINT8 Core,
IN OUT AP_DATA_TRANSFER *BufferInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetLocalApicIdForCore (
IN UINT32 TargetSocket,
IN UINT32 TargetCore,
OUT UINT32 *LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
ApUtilRunCodeOnAllLocalCoresAtEarly (
IN AP_TASK *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
);
VOID
RelinquishControlOfAllAPs (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetCsSelector (
IN UINT16 *Selector,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
SetIdtr (
IN IDT_BASE_LIMIT *IdtInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetIdtr (
IN IDT_BASE_LIMIT *IdtInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif /* _CPU_APIC_UTILITIES_H_ */

290
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@ -1,290 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU Reset API, and related functions and structures.
*
* Contains code that initialized the CPU after early reset.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_EARLY_INIT_H_
#define _CPU_EARLY_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
//----------------------------------------------------------------------------
// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
//
//----------------------------------------------------------------------------
#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
#define LOW_NODE_DEVICEID 24
#define NB_CAPABILITIES 0xE8 //Function 3 Registers
//----------------------------------------------------------------------------
// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
//
//----------------------------------------------------------------------------
/* All lengths are in bytes */
#define MICROCODE_TRIADE_SIZE 28
#define MICROCODE_HEADER_LENGTH 64
/**
* @page ucodeflag Microcode Patches Signature Guide
*
* We mark patches in the ROM with a signature so that they can be easily found
*
* @anchor Microcode Patch Signature
* @li @e Microcode Patch Signature @n
* Microcode patches are marked by adding a signature before patches in the ROM image to
* help identify where they are located.
* There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
* The other is '$UCODE4K', it indicates there's a following patch with 4K size.
* If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
*
*
*/
/// Microcode patch flag for replacement
typedef struct {
IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
} MICROCODE_PATCHES_FLAG;
#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
/* Offsets in UCODE PATCH Header */
/* Note: Header is 64 bytes */
#define DATE_CODE_OFFSET 0 // 4 bytes
#define PATCH_ID 4 // 4 bytes
#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
#define PROCESSOR_REV_ID 24 // 2 bytes
#define CHIPSET_1_REV_ID 26 // 1 byte
#define CHIPSET_2_REV_ID 27 // 1 byte
#define MICROCODE_PATCH_2K_SIZE 2048
#define MICROCODE_PATCH_4K_SIZE 4096
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
//----------------------------------------------------------------------------
// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
//
//----------------------------------------------------------------------------
/// A structure representing BrandId[15:0] from
/// CPUID Fn8000_0001_EBX
typedef struct {
UINT8 String1:4; ///< An index to a string value used to create the name string
UINT8 String2:4; ///< An index to a string value used to create the name string
UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
UINT8 Model:7; ///< A field used to create the model number in the name string
UINT8 Socket:4; ///< Specifies the package type
UINT8 Cores:4; ///< Identifies how many physical cores are present
} AMD_CPU_BRAND_DATA;
/// A structure containing string1 and string2 values
/// as well as information pertaining to their usage
typedef struct {
IN UINT8 Cores; ///< Appropriate number of physical cores
IN UINT8 Page; ///< This string's page number
IN UINT8 Index; ///< String index
IN UINT8 Socket; ///< Package type information
IN CONST CHAR8 *Stringstart; ///< The literal string
IN UINT8 Stringlength; ///< Number of characters in the string
} AMD_CPU_BRAND;
/// An entire CPU brand table.
typedef struct {
UINT8 NumberOfEntries; ///< The number of entries in the table.
CONST AMD_CPU_BRAND *Table; ///< The table entries.
} CPU_BRAND_TABLE;
//----------------------------------------------------------------------------
// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
//
//----------------------------------------------------------------------------
/// Microcode patch field definitions
typedef struct {
UINT32 DateCode; ///< Date of patch creation
UINT32 PatchID; ///< Patch level
UINT16 MicrocodePatchDataID; ///< Internal use only
UINT8 MicrocodePatchDataLength; ///< Internal use only
UINT8 InitializationFlag; ///< Internal use only
UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block
UINT32 Chipset1DeviceID; ///< Device ID of 1st Chipset device to match
UINT32 Chipset2DeviceID; ///< Device ID of 2nd Chipset device to match
UINT16 ProcessorRevisionID; ///< Equivalent ID
UINT8 Chipset1RevisionID; ///< Revision level of 1st Chipset device to match
UINT8 Chipset2RevisionID; ///< Revision level of 2nd Chipset device to match
UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required
UINT8 Reserved1[3]; ///< Reserved
UINT32 MatchRegister0; ///< Internal use only
UINT32 MatchRegister1; ///< Internal use only
UINT32 MatchRegister2; ///< Internal use only
UINT32 MatchRegister3; ///< Internal use only
UINT32 MatchRegister4; ///< Internal use only
UINT32 MatchRegister5; ///< Internal use only
UINT32 MatchRegister6; ///< Internal use only
UINT32 MatchRegister7; ///< Internal use only
UINT8 PatchDataBlock[896]; ///< Raw patch data
UINT8 Reserved2[896]; ///< Reserved
UINT8 X86CodePresent; ///< Boolean to determine if executable code exists
UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0
} MICROCODE_PATCH;
/// Two kilobyte array containing the raw
/// microcode patch binary data
typedef struct {
IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements
} MICROCODE_PATCHES;
/// Four kilobyte array containing the raw
/// microcode patch binary data
typedef struct {
IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements
} MICROCODE_PATCHES_4K;
/**
* Set down core register
*
* @CpuServiceInstances
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Socket Socket ID.
* @param[in] Module Module ID in socket.
* @param[in] LeveledCores Number of core.
* @param[in] CoreLevelMode Core level mode.
* @param[in] StdHeader Header for library and services.
*
* @retval TRUE Down Core register is updated.
* @retval FALSE Down Core register is not updated.
*/
typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
IN UINT32 *Socket,
IN UINT32 *Module,
IN UINT32 *LeveledCores,
IN CORE_LEVELING_TYPE CoreLevelMode,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a method
typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
/**
* Provide the interface to the Core Leveling Family Specific Services.
*
* Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
* Each supported Family must provide an implementation for all methods in this interface, even if the
* implementation is a CommonReturn().
*/
struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
UINT16 Revision; ///< Interface version
// Public Methods.
PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
};
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
// These are P U B L I C functions, used by IBVs
AGESA_STATUS
AmdCpuEarly (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig
);
// These are P U B L I C functions, used by AGESA
AGESA_STATUS
PmInitializationAtEarly (
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
LoadMicrocodePatch (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
GetPatchEquivalentId (
IN OUT UINT16 *ProcessorEquivalentId,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
ValidateMicrocode (
IN MICROCODE_PATCH *MicrocodePatchPtr,
IN UINT16 ProcessorEquivalentId,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetMicrocodeVersion (
OUT UINT32 *pMicrocodeVersion,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
AmdCpuEarlyInitializer (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
);
VOID
McaInitialization (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_EARLY_INIT_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU Register Table Related Functions
*
* Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 284995 $ @e \$Date: 2014-02-17 11:17:41 -0600 (Mon, 17 Feb 2014) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_REGISTERS_H_
#define _CPU_REGISTERS_H_
#include "cpuFamRegisters.h"
/*
*--------------------------------------------------------------
*
* M O D U L E S U S E D
*
*---------------------------------------------------------------
*/
/*
*--------------------------------------------------------------
*
* D E F I N I T I O N S / M A C R O S
*
*---------------------------------------------------------------
*/
#undef BIT0
#undef BIT1
#undef BIT2
#undef BIT3
#undef BIT4
#undef BIT5
#undef BIT6
#undef BIT7
#undef BIT8
#undef BIT9
#undef BIT10
#undef BIT10
#undef BIT11
#undef BIT12
#undef BIT13
#undef BIT14
#undef BIT15
#undef BIT16
#undef BIT17
#undef BIT18
#undef BIT19
#undef BIT20
#undef BIT21
#undef BIT22
#undef BIT23
#undef BIT24
#undef BIT25
#undef BIT26
#undef BIT27
#undef BIT28
#undef BIT29
#undef BIT30
#undef BIT31
#undef BIT32
#undef BIT33
#undef BIT34
#undef BIT35
#undef BIT36
#undef BIT37
#undef BIT38
#undef BIT39
#undef BIT40
#undef BIT41
#undef BIT42
#undef BIT43
#undef BIT44
#undef BIT45
#undef BIT46
#undef BIT47
#undef BIT48
#undef BIT49
#undef BIT40
#undef BIT41
#undef BIT42
#undef BIT43
#undef BIT44
#undef BIT45
#undef BIT46
#undef BIT47
#undef BIT48
#undef BIT49
#undef BIT50
#undef BIT51
#undef BIT52
#undef BIT53
#undef BIT54
#undef BIT55
#undef BIT56
#undef BIT57
#undef BIT58
#undef BIT59
#undef BIT60
#undef BIT61
#undef BIT62
#undef BIT63
#define BIT0 0x0000000000000001ull
#define BIT1 0x0000000000000002ull
#define BIT2 0x0000000000000004ull
#define BIT3 0x0000000000000008ull
#define BIT4 0x0000000000000010ull
#define BIT5 0x0000000000000020ull
#define BIT6 0x0000000000000040ull
#define BIT7 0x0000000000000080ull
#define BIT8 0x0000000000000100ull
#define BIT9 0x0000000000000200ull
#define BIT10 0x0000000000000400ull
#define BIT11 0x0000000000000800ull
#define BIT12 0x0000000000001000ull
#define BIT13 0x0000000000002000ull
#define BIT14 0x0000000000004000ull
#define BIT15 0x0000000000008000ull
#define BIT16 0x0000000000010000ull
#define BIT17 0x0000000000020000ull
#define BIT18 0x0000000000040000ull
#define BIT19 0x0000000000080000ull
#define BIT20 0x0000000000100000ull
#define BIT21 0x0000000000200000ull
#define BIT22 0x0000000000400000ull
#define BIT23 0x0000000000800000ull
#define BIT24 0x0000000001000000ull
#define BIT25 0x0000000002000000ull
#define BIT26 0x0000000004000000ull
#define BIT27 0x0000000008000000ull
#define BIT28 0x0000000010000000ull
#define BIT29 0x0000000020000000ull
#define BIT30 0x0000000040000000ull
#define BIT31 0x0000000080000000ull
#define BIT32 0x0000000100000000ull
#define BIT33 0x0000000200000000ull
#define BIT34 0x0000000400000000ull
#define BIT35 0x0000000800000000ull
#define BIT36 0x0000001000000000ull
#define BIT37 0x0000002000000000ull
#define BIT38 0x0000004000000000ull
#define BIT39 0x0000008000000000ull
#define BIT40 0x0000010000000000ull
#define BIT41 0x0000020000000000ull
#define BIT42 0x0000040000000000ull
#define BIT43 0x0000080000000000ull
#define BIT44 0x0000100000000000ull
#define BIT45 0x0000200000000000ull
#define BIT46 0x0000400000000000ull
#define BIT47 0x0000800000000000ull
#define BIT48 0x0001000000000000ull
#define BIT49 0x0002000000000000ull
#define BIT50 0x0004000000000000ull
#define BIT51 0x0008000000000000ull
#define BIT52 0x0010000000000000ull
#define BIT53 0x0020000000000000ull
#define BIT54 0x0040000000000000ull
#define BIT55 0x0080000000000000ull
#define BIT56 0x0100000000000000ull
#define BIT57 0x0200000000000000ull
#define BIT58 0x0400000000000000ull
#define BIT59 0x0800000000000000ull
#define BIT60 0x1000000000000000ull
#define BIT61 0x2000000000000000ull
#define BIT62 0x4000000000000000ull
#define BIT63 0x8000000000000000ull
/// CPUID related registers
#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information
#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul
#define CPUID_ASSOCIATIVITY_DISABLED 0x00
#define CPUID_ASSOCIATIVITY_1_WAY 0x01
#define CPUID_ASSOCIATIVITY_2_WAY 0x02
#define CPUID_ASSOCIATIVITY_4_WAY 0x04
#define CPUID_ASSOCIATIVITY_8_WAY 0x06
#define CPUID_ASSOCIATIVITY_16_WAY 0x08
#define CPUID_ASSOCIATIVITY_32_WAY 0x0A
#define CPUID_ASSOCIATIVITY_48_WAY 0x0B
#define CPUID_ASSOCIATIVITY_64_WAY 0x0C
#define CPUID_ASSOCIATIVITY_96_WAY 0x0D
#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
#define CPUID_ASSOCIATIVITY_FULLY 0x0F
#define AMD_CPUID_TLB_L1Cache 0x80000005ul
#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul
#define AMD_CPUID_APM 0x80000007ul
#define LOCAL_APIC_ID 24
#define LOGICAL_PROCESSOR_COUNT 16
#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count
/// CPU Logical ID Transfer
typedef struct {
UINT32 RawId; ///< RawID
UINT64 LogicalId; ///< LogicalID
} CPU_LOGICAL_ID_XLAT;
/// Logical CPU ID Table
typedef struct {
IN UINT32 Elements; ///< Number of Elements
IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
} LOGICAL_ID_TABLE;
// MSRs
// ------------------------
#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR
#define MSR_MCG_CAP 0x00000179ul
#define DBG_CTL_MSR 0x000001D9ul
#define MSR_MC0_CTL 0x00000400ul
#define MSR_MC0_STATUS 0x00000401ul
#define MSR_MC0_MISC 0x00000403ul
#define MSR_MC1_MISC 0x00000407ul
#define MSR_MC2_MISC 0x0000040Bul
#define MSR_MC4_CTL 0x00000410ul
#define MSR_MC4_MISC0 0x00000413ul
#define MSR_MC5_MISC 0x00000417ul
#define MSR_MC4_MISC1 0xC0000408ul
#define MSR_MC5_STATUS 0x00000415ul
#define MSR_MC6_STATUS 0x00000419ul
#define MSR_APIC_BAR 0x0000001Bul
#define MSR_PATCH_LEVEL 0x0000008Bul
#define CPUID_LONG_MODE_ADDR 0x80000008ul
#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul
#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul
#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul
#define MSR_PATCH_LOADER 0xC0010020ul
/// Patch Loader Register
typedef struct {
UINT64 PatchBase:32; ///< Linear address of patch header address block
UINT64 SBZ:32; ///< Should be zero
} PATCH_LOADER_MSR;
#define MSR_SYS_CFG 0xC0010010ul // SYSCFG - F15 Shared
#define MSR_TOM2 0xC001001Dul // TOP_MEM2 - F15 Shared
#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask
#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask
#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask
#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask
#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features
#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features
#define MSR_HDT_CFG 0xC001100Aul
#define MSR_HWCR 0xC0010015ul
#define MSR_NB_CFG 0xC001001Ful // NB Config
#define CPU_WDT_CFG 0xC0010074ul
#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46]
#define INIT_APIC_CPUID_LO 0x00400000ul // [54]
#define MSR_CU_SPMCTL 0xC0010281ul
#define MSR_CpuWdtCfg 0xC0010074ul // CPU Watchdog Timer
#define MSR_LS_CFG 0xC0011020ul
#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared
#define MSR_DC_CFG 0xC0011022ul
#define MSR_ME_CFG 0xC0011029ul
#define MSR_BU_CFG 0xC0011023ul
#define MSR_CU_CFG 0xC0011023ul // F15 Shared
#define MSR_DE_CFG 0xC0011029ul // F15 Shared
#define MSR_BU_CFG2 0xC001102Aul
#define MSR_CU_CFG2 0xC001102Aul // F15 Shared
#define MSR_BU_CFG3 0xC001102Bul
#define MSR_CU_CFG3 0xC001102Bul // F15 Shared
#define MSR_LS_CFG2 0xC001102Dul
#define MSR_CU_PFTCFG 0xC001102Ful
#define MSR_IBS_OP_DATA3 0xC0011037ul
#define MSR_C001_1070 0xC0011070ul // F15 Shared
#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register
#define MSR_CPUID_NAME_STRING1 0xC0010031ul
#define MSR_CPUID_NAME_STRING2 0xC0010032ul
#define MSR_CPUID_NAME_STRING3 0xC0010033ul
#define MSR_CPUID_NAME_STRING4 0xC0010034ul
#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register
#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register
#define MSR_BIST 0xC0010060ul // BIST Results register
#define MSR_OSVW_ID_Length 0xC0010140ul
#define MSR_OSVW_Status 0xC0010141ul
#define MSR_NB_PERF_CTL0 0xC0010240ul
#define MSR_NB_PERF_CTR0 0xC0010241ul
#define MSR_NB_PERF_CTL1 0xC0010242ul
#define MSR_NB_PERF_CTR1 0xC0010243ul
#define MSR_NB_PERF_CTL2 0xC0010244ul
#define MSR_NB_PERF_CTR2 0xC0010245ul
#define MSR_NB_PERF_CTL3 0xC0010246ul
#define MSR_NB_PERF_CTR3 0xC0010247ul
#define CU_SPMCTL 0xC0010281ul // Streaming Performance Monitor Control
#define MSR_PERF_CONTROL3 0xC0010003ul // Performance control register number 3
#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3
#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits
#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the
// CAR Corruption
// FUNC_0 registers
// ----------------
#define LINK_INIT_CTRL 0x6C
#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
#define LINK_INIT_COLD_RST_DET BIT4
#define LINK_INIT_BIOS_RST_DET_0 BIT5
#define LINK_INIT_BIOS_RST_DET_1 BIT9
#define LINK_INIT_BIOS_RST_DET_2 BIT10
#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10
#define EXTENDED_NODE_ID 0x160
#define CORE_CTRL 0x1DC
#define CORE_CTRL_CORE1_EN 0x00000002ul
#define CORE_CTRL_CORE2_EN 0x00000004ul
#define CORE_CTRL_CORE3_EN 0x00000008ul
#define CORE_CTRL_CORE4_EN 0x00000010ul
#define CORE_CTRL_CORE5_EN 0x00000020ul
#define CORE_CTRL_CORE6_EN 0x00000040ul
#define CORE_CTRL_CORE7_EN 0x00000080ul
#define CORE_CTRL_CORE8_EN 0x00000100ul
#define CORE_CTRL_CORE9_EN 0x00000200ul
// FUNC_3 registers
// ----------------
#define HARDWARE_THERMAL_CTRL_REG 0x64
#define SOFTWARE_THERMAL_CTRL_REG 0x68
#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
#define ACPI_PSC_4_REG 0x84
#define NB_CFG_HIGH_REG 0x8C
#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
#define MULTI_NODE_CPU 29
#define CPUID_FMR 0xFC // Family / Model registers
#define DOWNCORE_CTRL 0x190 // Downcore Control Register
#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
// FUNC_4 registers
// ----------------
/* Native Die CPUID Register F4x160 */
#define NATIVE_DIE_CPUID_REG 0x160
#define NATIVE_DIE_CPUID_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, NATIVE_DIE_CPUID_REG))
/// Native Die CPUID PCI Register
typedef struct {
UINT32 Stepping:4; ///< Stepping
UINT32 BaseModel:4; ///< Base Model
UINT32 BaseFamily:4; ///< Base Family
UINT32 :4; ///< Reserved
UINT32 ExtModel:4; ///< Extended Model
UINT32 ExtFamily:8; ///< Extended Family
UINT32 :4; ///< Reserved
} NATIVE_DIE_CPUID_REGISTER;
// FUNC_5 registers
// ----------------
#define COMPUTE_UNIT_STATUS 0x80
#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
// Misc. defines.
#define PCI_DEV_BASE 24
#define CPUID_STEPPING_MASK 0x0000000Ful
#define CPUID_BASE_MODEL_MASK 0x000000F0ul
#define CPUID_BASE_FAMILY_MASK 0x00000F00ul
#define CPUID_EXT_MODEL_MASK 0x000F0000ul
#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
#define TN_SOCKET_FP2 0
#define TN_SOCKET_FS1 1
#define TN_SOCKET_FM2 2
#define KV_SOCKET_FP3 0
#define KV_SOCKET_FM2r2 1
#define SOCKET_IGNORE 0xF
#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
#define APIC_EXT_BRDCST_MASK 0x000E0000ul
#define APIC_ENABLE_BIT 0x00000800ul
#define LOCAL_APIC_ADDR 0xFEE00000ul
#define INT_CMD_REG_LO 0x300
#define INT_CMD_REG_HI 0x310
#define REMOTE_MSG_REG 0x380
#define REMOTE_READ_REG 0xC0
#define APIC_ID_REG 0x20
#define APIC20_ApicId 24
#define CMD_REG_TO_READ_DATA 0x338
#define MAX_CORE_ID_SIZE 8
#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
/*-------------------------
* Default definitions
*-------------------------
*/
#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul
#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul
#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul
#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul
#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul
#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul
#define DOWNCORE_MASK_SEVEN 0xFFFFFF80ul
#define DOWNCORE_MASK_EIGHT 0xFFFFFF00ul
#define DOWNCORE_MASK_TEN 0xFFFFFC00ul
#define DOWNCORE_MASK_TWELVE 0xFFFFF000ul
#define DOWNCORE_MASK_FOURTEEN 0xFFFFC000ul
#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul
#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul
#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul
#define DOWNCORE_MASK_FIVE_COMPUTE_UNIT 0xFFFFFEAAul
#define DOWNCORE_MASK_SIX_COMPUTE_UNIT 0xFFFFFAAAul
#define DOWNCORE_MASK_SEVEN_COMPUTE_UNIT 0xFFFFEAAAul
#define DOWNCORE_MASK_EIGHT_COMPUTE_UNIT 0xFFFFAAAAul
#define DELIVERY_STATUS BIT13
#define REMOTE_READ_STAT_MASK 0x00030000ul
#define REMOTE_DELIVERY_PENDING 0x00010000ul
#define REMOTE_DELIVERY_DONE 0x00020000ul
/*
* --------------------------------------------------------------------------------------
*
* D E F I N E S / T Y P E D E F S / S T R U C T U R E S
*
* --------------------------------------------------------------------------------------
*/
/// CpuEarly param type
typedef struct {
IN UINT8 MemInitPState; ///< Pstate value during memory initial
IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options
} AMD_CPU_EARLY_PARAMS;
/// CPUID
typedef enum {
REG_EAX, ///< EAX
REG_EBX, ///< EBX
REG_ECX, ///< ECX
REG_EDX ///< EDX
} CPUID_REG;
#endif // _CPU_REGISTERS_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD Heap Manager and Heap Allocation APIs, and related functions.
*
* Contains code that initialize, maintain, and allocate the heap space.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 296129 $ @e \$Date: 2014-06-23 09:45:14 -0500 (Mon, 23 Jun 2014) $
*
*/
/*
******************************************************************************
*
* Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _HEAP_MANAGER_H_
#define _HEAP_MANAGER_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
#define AMD_MTRR_VARIABLE_BASE0 0x200
#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
#define AMD_HEAP_START_ADDRESS 0x400000ul
#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul
#define AMD_HEAP_SIZE_PER_CORE 0x010000ul
#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul
#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800)
#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value)
#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20
#define AMD_HEAP_RAM_ADDRESS 0xB0000ul
#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP'
#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared
///Heap Manager Life cycle
#define HEAP_DO_NOT_EXIST_YET 1
#define HEAP_LOCAL_CACHE 2
#define HEAP_TEMP_MEM 3
#define HEAP_SYSTEM_MEM 4
#define HEAP_DO_NOT_EXIST_ANYMORE 5
#define HEAP_S3_RESUME 6
#define HEAP_RUNTIME_SYSTEM_MEM 7
///Heap callout
#define HEAP_CALLOUT_BOOTTIME 0
#define HEAP_CALLOUT_RUNTIME 1
#define AMD_MTRR_FIX64k_00000 0x250
#define AMD_MTRR_FIX16k_80000 0x258
#define AMD_MTRR_FIX16k_A0000 0x259
#define AMD_MTRR_FIX4k_C0000 0x268
#define AMD_MTRR_FIX4k_C8000 0x269
#define AMD_MTRR_FIX4k_D0000 0x26A
#define AMD_MTRR_FIX4k_D8000 0x26B
#define AMD_MTRR_FIX4k_E0000 0x26C
#define AMD_MTRR_FIX4k_E8000 0x26D
#define AMD_MTRR_FIX4k_F0000 0x26E
#define AMD_MTRR_FIX4k_F8000 0x26F
#define AMD_MTRR_FIX64K_WB_DRAM 0x1E
#define AMD_MTRR_FIX64K_WT_DRAM 0x1C
#define AMD_MTRR_FIX64K_UC_DRAM 0x18
#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull
#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/// Allocate Heap Parameters
typedef struct _ALLOCATE_HEAP_PARAMS {
UINT32 RequestedBufferSize; ///< Size of buffer.
UINT32 BufferHandle; ///< An unique ID of buffer.
UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
UINT8 *BufferPtr; ///< Pointer to buffer.
} ALLOCATE_HEAP_PARAMS;
/// Locate Heap Parameters
typedef struct _LOCATE_HEAP_PTR {
UINT32 BufferHandle; ///< An unique ID of buffer.
UINT32 BufferSize; ///< Data buffer size.
UINT8 *BufferPtr; ///< Pointer to buffer.
} LOCATE_HEAP_PTR;
/// Heap Node Header
typedef struct _BUFFER_NODE {
UINT32 BufferHandle; ///< An unique ID of buffer.
UINT32 BufferSize; ///< Size of buffer.
UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
UINT8 PadSize; ///< Size of pad.
UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
} BUFFER_NODE;
/// Heap Manager
typedef struct _HEAP_MANAGER {
UINT32 Signature; ///< a signature to indicate if the heap is valid.
UINT32 UsedSize; ///< Used size of heap.
UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
} HEAP_MANAGER;
/// AGESA Buffer Handles (These are reserved)
typedef enum {
AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine.
AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3
AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information
AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information
EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A017 buffer handle to Event Log
IDS_CONTROL_HANDLE, ///< Assign 0x000A018 buffer handle to AmdIds routine.
IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to be used for HDTOUT support.
IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01A buffer handle to Performance analysis
AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to be used for PCIe support
AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01C buffer handle to be used for memory data structure
AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GNB SMU configuration
AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A01E buffer handle to be used for TT fuse table
AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for Gfx platform configuration
AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A020 buffer handle for GNB general purpose data block
AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A021 buffer handle for 2D training
AMD_MEM_2D_RD_WR_HANDLE, ///< Assign 0x000A022 buffer handle for 2D Read/Write training
AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A023 buffer handle to be used for GNB IOMMU scratch memory
AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A024 buffer handle for memory data saved right after memory init
AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training Eye RIM Search
AMD_MEM_2D_RD_WR_RIM_HANDLE, ///< Assign 0x000A026 buffer handle for 2D Read/Write training Eye RIM Search
AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A027 buffer handle for an NB P-state workaround
AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A028 buffer handle for CRAT Memory affinity component structure
AMD_SKIP_MEM_S3_SAVE, ///< Assign 0x000A029 buffer handle for the flag to skip memory S3 save
AMD_SCS_SMU_RAM_INFO, ///< Assign 0x000A02A buffer handle for keeping the result of SMU SCS service
AMD_SCS_HWP0_FREQ, ///< Assign 0x000A02B buffer handler for keeping frequency of HWP0
AMD_IS_FEATURE_ENABLED, ///< Assign 0x000A02C buffer handle for keeping the result of IsFeatureEnabled
AMD_MEM_DATAEYE_WORK_AREA_HANDLE, ///< Assign 0x000A02D buffer handle for Composite Data Eye Compression Work Area
AMD_GNB_SAMU_PATCH_HANDLE, ///< Assign 0x000A02E buffer handle for Samu patch buffer
AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, ///< Assign 0x000A02F buffer handle for Samu boot control buffer
AMD_GNB_ACP_ENGINE_HANDLE, ///< Assign 0x000A030 buffer handle for GNB ACP engine buffer
AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE, ///< Assign 0x000A031 buffer handle for PMU SRAM Message Block buffer
AMD_GNB_SMU_TABLE_HANDLE, ///< Assign 0x000A032 buffer handle for GNB SMU table buffer
AMD_GNB_CRAT_HSA_TABLE_HANDLE, ///< Assign 0x000A033 buffer handle for GNB CRAT HSA unit table
AMD_GNB_BUILD_OPTIONS_HANDLE, ///< Assign 0x000A034 buffer handle for GNB build options
AMD_S3_FINAL_RESTORE_HANDLE, ///< Assign 0x000A035 buffer handle to AmdS3FinalRestore routine.
AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset
AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv
IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table
IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR'
IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table
IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save
IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save
IDS_EXTEND_HANDLE = 0x54584549, ///< 'IEXT' Handle for IDS extend module
IDS_TEMP_DATA_HANDLE = 0x504D5459, ///< 'ITMP' Handle for IDS temp data
} AGESA_BUFFER_HANDLE;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
AGESA_STATUS
HeapManagerInit (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
HeapAllocateBuffer (
IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
HeapDeallocateBuffer (
IN UINT32 BufferHandle,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
HeapLocateBuffer (
IN OUT LOCATE_HEAP_PTR *LocateHeap,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT64
HeapGetBaseAddress (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
EventLogInitialization (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _HEAP_MANAGER_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD FCH Component
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _AMD_FCH_H_
#define _AMD_FCH_H_
typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr);
typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg);
/// FCH API build options
typedef struct {
FCH_INIT *InitReset; ///< InitReset
FCH_INIT *InitResetConstructor; ///< InitResetConstructor
FCH_INIT *InitEnv; ///< InitEnv
FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor
FCH_INIT *InitMid; ///< InitMid
FCH_INIT *InitMidConstructor; ///< InitMidConstructor
FCH_INIT *InitLate; ///< InitLate
FCH_INIT *InitLateConstructor; ///< InitLateConstructor
} BLDOPT_FCH_FUNCTION;
#endif

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/* $NoKeywords:$ */
/**
* @file
*
* FCH ACPI lib
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#ifndef _FCH_ACPILIB_H_
#define _FCH_ACPILIB_H_
///
/// RSDP - ACPI 2.0 table RSDP
///
typedef struct _RSDP_HEADER {
UINT64 Signature; ///< RSDP signature "RSD PTR"
UINT8 CheckSum; ///< checksum of the first 20 bytes
UINT8 OEMID[6]; ///< OEM ID
UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
UINT32 RsdtAddress; ///< physical address of RSDT
UINT32 Length; ///< total length of RSDP (including extended part)
UINT64 XsdtAddress; ///< physical address of XSDT
UINT8 ExtendedCheckSum; ///< chechsum of whole table
UINT8 Reserved[3]; ///< Reserved
} RSDP_HEADER;
///
/// DESCRIPTION_HEADER - ACPI common table header
///
typedef struct _DESCRIPTION_HEADER {
UINT32 Signature; ///< ACPI signature (4 ASCII characters)
UINT32 Length; ///< Length of table, in bytes, including header
UINT8 Revision; ///< ACPI Specification minor version #
UINT8 CheckSum; ///< To make sum of entire table == 0
UINT8 OemId[6]; ///< OEM identification
UINT8 OemTableId[8]; ///< OEM table identification
UINT32 OemRevision; ///< OEM revision number
UINT32 CreatorId; ///< ASL compiler vendor ID
UINT32 CreatorRevision; ///< ASL compiler revision number
} DESCRIPTION_HEADER;
///
/// _AcpiRegWrite - ACPI MMIO register R/W structure
///
typedef struct _ACPI_REG_WRITE {
UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
UINT8 MmioReg; /// MmioReg : Register index
UINT8 DataAndMask; /// DataANDMask : AND Register Data
UINT8 DataOrMask; /// DataOrMask : Or Register Data
} ACPI_REG_WRITE;
VOID* AcpiLocateTable (IN UINT32 Signature);
VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
#endif

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/* $NoKeywords:$ */
/**
* @file
*
* FCH BIOS Ram usage
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#ifndef _FCH_BIOS_RAM_USAGE_H_
#define _FCH_BIOS_RAM_USAGE_H_
#define RESTORE_MEMORY_CONTROLLER_START 0
#define XHCI_REGISTER_BAR00 0xD0
#define XHCI_REGISTER_BAR01 0xD1
#define XHCI_REGISTER_BAR02 0xD2
#define XHCI_REGISTER_BAR03 0xD3
#define XHCI_REGISTER_04H 0xD4
#define XHCI_REGISTER_0CH 0xD5
#define XHCI_REGISTER_3CH 0xD6
#define XHCI1_REGISTER_BAR00 0xE0
#define XHCI1_REGISTER_BAR01 0xE1
#define XHCI1_REGISTER_BAR02 0xE2
#define XHCI1_REGISTER_BAR03 0xE3
#define XHCI1_REGISTER_04H 0xE4
#define XHCI1_REGISTER_0CH 0xE5
#define XHCI1_REGISTER_3CH 0xE6
#define RTC_WORKAROUND_DATA_START 0xF0
#define BOOT_TIME_FLAG_SEC 0xF8
#define BOOT_TIME_FLAG_INT19 0xFC
#endif

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@ -1,477 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH routine definition
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*****************************************************************************
*
* Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef _FCH_DEF_H_
#define _FCH_DEF_H_
UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);
VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader);
///
/// Fch Ab Routines
///
/// Pei Phase
///
VOID FchInitResetAb (IN VOID* FchDataPtr);
VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvAb (IN VOID* FchDataPtr);
VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
VOID FchInitMidAb (IN VOID* FchDataPtr);
VOID FchInitLateAb (IN VOID* FchDataPtr);
///
/// Other Public Routines
///
VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchAbLateProgram (IN VOID* FchDataPtr);
///
/// Fch Pcie Routines
///
/// Pei Phase
///
VOID FchInitResetPcie (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvPcie (IN VOID* FchDataPtr);
VOID FchInitMidPcie (IN VOID* FchDataPtr);
VOID FchInitLatePcie (IN VOID* FchDataPtr);
VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
///
/// Fch Gpp Routines
///
/// Pei Phase
///
VOID FchInitResetGpp (IN VOID* FchDataPtr);
VOID ProgramFchGppInitReset (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader);
///
/// Dxe Phase
///
VOID FchInitEnvGpp (IN VOID* FchDataPtr);
VOID FchInitMidGpp (IN VOID* FchDataPtr);
VOID FchInitLateGpp (IN VOID* FchDataPtr);
///
/// Common Gpp Routines
///
VOID ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppForceGen1 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppForceGen2 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
UINT8 GppPortPollingLtssm (IN FCH_GPP *FchGpp, IN UINT8 ActivePorts, IN BOOLEAN IsGen2, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GppGen2Workaround (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppPortInit (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppPortInitPhaseII (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppPortInitS3Phase (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
UINT32 GppGetFchTempBus (IN AMD_CONFIG_PARAMS *StdHeader);
///
/// Fch Azalia Routines
///
/// Pei Phase
///
VOID FchInitResetAzalia (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
VOID FchInitMidAzalia (IN VOID *FchDataPtr);
VOID FchInitLateAzalia (IN VOID *FchDataPtr);
///
/// Fch GEC Routines
///
/// Pei Phase
///
VOID FchInitResetGec (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvGec (IN VOID* FchDataPtr);
VOID FchInitMidGec (IN VOID* FchDataPtr);
VOID FchInitLateGec (IN VOID* FchDataPtr);
///
/// Other Public Routines
///
VOID FchInitGecController (IN VOID* FchDataPtr);
VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
///
/// Fch HwAcpi Routines
///
/// Pei Phase
///
VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
///
/// Other Public Routines
///
VOID HpetInit (IN VOID *FchDataPtr);
VOID C3PopupSetting (IN VOID *FchDataPtr);
VOID MtC1eEnable (IN VOID *FchDataPtr);
VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
VOID StressResetModeLate (IN VOID *FchDataPtr);
///
/// Fch Hwm Routines
///
/// Pei Phase
///
VOID FchInitResetHwm (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvHwm (IN VOID* FchDataPtr);
VOID FchInitMidHwm (IN VOID* FchDataPtr);
VOID FchInitLateHwm (IN VOID* FchDataPtr);
///
/// Other Public Routines
///
VOID HwmInitRegister (IN VOID* FchDataPtr);
VOID HwmProcessParameter (IN VOID* FchDataPtr);
VOID HwmSetRegister (IN VOID* FchDataPtr);
VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr);
VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
VOID HwmGetRawData (IN VOID* FchDataPtr);
VOID HwmCaculate (IN VOID* FchDataPtr);
VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr);
VOID FchECfancontrolservice (IN VOID* FchDataPtr);
///
/// Fch Ide Routines
///
VOID FchInitEnvIde (IN VOID* FchDataPtr);
VOID FchInitMidIde (IN VOID* FchDataPtr);
VOID FchInitLateIde (IN VOID* FchDataPtr);
///
/// Fch Imc Routines
///
/// Pei Phase
///
VOID FchInitResetImc (IN VOID *FchDataPtr);
VOID FchInitResetEc (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvImc (IN VOID *FchDataPtr);
VOID FchInitMidImc (IN VOID *FchDataPtr);
VOID FchInitLateImc (IN VOID *FchDataPtr);
VOID FchInitEnvEc (IN VOID *FchDataPtr);
VOID FchInitMidEc (IN VOID *FchDataPtr);
VOID FchInitLateEc (IN VOID *FchDataPtr);
///
/// Other Public Routines
///
VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ImcSleep (IN VOID *FchDataPtr);
VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr);
VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
VOID ImcWakeup (IN VOID *FchDataPtr);
VOID ImcIdle (IN VOID *FchDataPtr);
BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
VOID ImcCrashReset (IN VOID *FchDataPtr);
VOID SoftwareDisableImc (IN VOID *FchDataPtr);
///
/// Fch Ir Routines
///
/// Dxe Phase
///
VOID FchInitEnvIr (IN VOID* FchDataPtr);
VOID FchInitMidIr (IN VOID* FchDataPtr);
VOID FchInitLateIr (IN VOID* FchDataPtr);
///
/// Fch Pcib Routines
///
/// Pei Phase
///
VOID FchInitResetPcib (IN VOID* FchDataPtr);
VOID FchInitResetPcibPort80Enable (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvPcib (IN VOID* FchDataPtr);
VOID FchInitMidPcib (IN VOID* FchDataPtr);
VOID FchInitLatePcib (IN VOID* FchDataPtr);
///
/// Fch SATA Routines
///
/// Pei Phase
///
VOID FchInitResetSata (IN VOID *FchDataPtr);
VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitMidSata (IN VOID *FchDataPtr);
VOID FchInitEnvSata (IN VOID *FchDataPtr);
VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
VOID FchInitLateSata (IN VOID *FchDataPtr);
VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
VOID FchInitMidSataIde (IN VOID *FchDataPtr);
VOID FchInitLateSataIde (IN VOID *FchDataPtr);
VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
VOID FchSataGpioInitial (IN VOID *FchDataPtr);
VOID SataBar5RegSet (IN VOID *FchDataPtr);
VOID SataSetPortGenMode (IN VOID *FchDataPtr);
VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchSataDriveFpga (IN VOID *FchDataPtr);
VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr);
///
/// FCH USB Controller Public Function
///
/// Pei Phase
///
VOID FchInitResetUsb (IN VOID *FchDataPtr);
VOID FchInitResetOhci (IN VOID *FchDataPtr);
VOID FchInitResetEhci (IN VOID *FchDataPtr);
VOID FchInitResetXhci (IN VOID *FchDataPtr);
VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvUsb (IN VOID *FchDataPtr);
VOID FchInitMidUsb (IN VOID *FchDataPtr);
VOID FchInitLateUsb (IN VOID *FchDataPtr);
VOID FchInitEnvUsbOhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci (IN VOID *FchDataPtr);
VOID FchInitLateUsbOhci (IN VOID *FchDataPtr);
VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci1 (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci2 (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci3 (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci4 (IN VOID *FchDataPtr);
VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr);
///
/// Other Public Routines
///
VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
///
/// Fch Sd Routines
///
VOID FchInitEnvSd (IN VOID *FchDataPtr);
VOID FchInitMidSd (IN VOID *FchDataPtr);
VOID FchInitLateSd (IN VOID *FchDataPtr);
///
/// Other Public Routines
///
VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
///
/// Fch Spi Routines
///
/// Pei Phase
///
VOID FchInitResetSpi (IN VOID *FchDataPtr);
VOID FchInitResetLpc (IN VOID *FchDataPtr);
VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvSpi (IN VOID *FchDataPtr);
VOID FchInitMidSpi (IN VOID *FchDataPtr);
VOID FchInitLateSpi (IN VOID *FchDataPtr);
VOID FchInitEnvLpc (IN VOID *FchDataPtr);
VOID FchInitMidLpc (IN VOID *FchDataPtr);
VOID FchInitLateLpc (IN VOID *FchDataPtr);
VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
///
/// Other Public Routines
///
VOID FchSpiUnlock (IN VOID *FchDataPtr);
VOID FchSpiLock (IN VOID *FchDataPtr);
/*--------------------------- Documentation Pages ---------------------------*/
VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID TurnOffCG2 (OUT VOID);
VOID BackUpCG2 (OUT VOID);
VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID AcLossControl (IN UINT8 AcLossControlValue);
VOID FchVgaInit (OUT VOID);
VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
VOID ValidateFchVariant (IN VOID *FchDataPtr);
VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
BOOLEAN IsGCPU (IN VOID *FchDataPtr);
BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
AGESA_STATUS
FchSpiTransfer (
IN UINT8 PrefixCode,
IN UINT8 Opcode,
IN OUT UINT8 *DataPtr,
IN UINT8 *AddressPtr,
IN UINT8 Length,
IN BOOLEAN WriteFlag,
IN BOOLEAN AddressFlag,
IN BOOLEAN DataFlag,
IN BOOLEAN FinishedFlag
);
BOOLEAN
FchPlatformSpiQe (
IN VOID *FchDataPtr
);
#endif

2285
src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h
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File diff suppressed because it is too large Load Diff

118
src/vendorcode/amd/pi/00630F01/Proc/Fch/FchPlatform.h
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@ -1,118 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH platform definition
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#ifndef _FCH_PLATFORM_H_
#define _FCH_PLATFORM_H_
#define MAX_SATA_PORTS 8
#include "AGESA.h"
#ifndef FCHOEM_ACPI_RESTORE_SWSMI
#define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
#define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
#define FCHOEM_ENABLE_ACPI_SWSMI 0xA0
#define FCHOEM_DISABLE_ACPI_SWSMI 0xA1
#define FCHOEM_START_TIMER_SMI 0xBC
#define FCHOEM_STOP_TIMER_SMI 0xBD
#endif
#ifndef FCHOEM_SPI_UNLOCK_SWSMI
#define FCHOEM_SPI_UNLOCK_SWSMI 0xAA
#endif
#ifndef FCHOEM_SPI_LOCK_SWSMI
#define FCHOEM_SPI_LOCK_SWSMI 0xAB
#endif
#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
#define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000ul
#endif
#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
#define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0ul
#endif
#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
#define FCHOEM_ACPI_BYTE_CHECHSUM 0x100
#endif
#ifndef FCHOEM_IO_DELAY_PORT
#define FCHOEM_IO_DELAY_PORT 0x80
#endif
#ifndef FCHOEM_OUTPUT_DEBUG_PORT
#define FCHOEM_OUTPUT_DEBUG_PORT 0x80
#endif
#define FCH_PCIRST_BASE_IO 0xCF9
#define FCH_PCI_RESET_COMMAND06 0x06
#define FCH_PCI_RESET_COMMAND0E 0x0E
#define FCH_KBDRST_BASE_IO 0x64
#define FCH_KBC_RESET_COMMAND 0xFE
#define FCH_ROMSIG_BASE_IO 0x20000l
#define FCH_ROMSIG_SIGNATURE 0x55AA55AAul
#define FCH_MAX_TIMER 0xFFFFFFFFul
#define FCH_GEC_INTERNAL_REG 0x6804
#define FCH_HPET_REG_MASK 0xFFFFF800ul
#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000ul
#ifndef FCHOEM_ELAPSED_TIME_UNIT
#define FCHOEM_ELAPSED_TIME_UNIT 28
#endif
#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
#define FCHOEM_ELAPSED_TIME_DIVIDER 100
#endif
#include "Fch.h"
#include "amdlib.h"
#include "FchCommonCfg.h"
#include "AcpiLib.h"
#include "FchDef.h"
#include "FchBiosRamUsage.h"
#include "AmdFch.h"
extern BUILD_OPT_CFG UserOptions;
#endif // _FCH_PLATFORM_H_

80
src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDebugPrint.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Integrated Debug Print Routines
*
* Contains all functions related to IDS Debug Print
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_DEBUGPRINT_H_
#define _IDS_DEBUGPRINT_H_
///Debug String End flag
#define DEBUG_STRING_END_FLAG (0x0)
/// return status for debug print
typedef enum {
IDS_DEBUG_PRINT_SUCCESS = 0, ///< success
IDS_DEBUG_PRINT_BUFFER_OVERFLOW, ///< Bufer overflow
} IDS_DEBUG_PRINT_STATUS;
/// Private datas for debug print
typedef struct _IDS_DEBUG_PRINT_PRIVATE_DATA {
BOOLEAN saveContext; /// save context
} IDS_DEBUG_PRINT_PRIVATE_DATA;
typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_SUPPORT) (VOID);
typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_FILTER) (UINT64 *Filter);
typedef VOID (*PF_IDS_DEBUG_PRINT_PRINT) (CHAR8 *Buffer, UINTN BufferSize, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate);
typedef VOID (*PF_IDS_DEBUG_INIT_PRIVATE_DATA) (UINT64 flag, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate);
/// Debug print Hw layer service class
typedef struct _IDS_DEBUG_PRINT {
PF_IDS_DEBUG_PRINT_SUPPORT support; ///Check if support
PF_IDS_DEBUG_PRINT_FILTER customfilter; ///Get if any customize filters
PF_IDS_DEBUG_INIT_PRIVATE_DATA InitPrivateData; ///Init private data
PF_IDS_DEBUG_PRINT_PRINT print; ///Print data to Hw layer
} IDS_DEBUG_PRINT;
VOID
GetDebugPrintList (
IN OUT CONST IDS_DEBUG_PRINT ***pIdsDebugPrintListPtr
);
#endif //_IDS_DEBUGPRINT_H_

119
src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpHdtout.h
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@ -1,119 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Integrated Debug Debug_library Routines
*
* Contains all functions related to HDTOUT
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_HDTOUT_H_
#define _IDS_HDTOUT_H_
#define HDTOUT_VERSION 0x0200
/// HDTOUT command
#define HDTOUT_COMMAND 0x99cc
#define HDTOUT_INIT (0x10BF0000ul | HDTOUT_COMMAND)
#define HDTOUT_ASSERT (0xA0BF0000ul | HDTOUT_COMMAND)
#define HDTOUT_EXIT (0xE0BF0000ul | HDTOUT_COMMAND)
#define HDTOUT_PRINT (0xC0BF0000ul | HDTOUT_COMMAND)
#define HDTOUT_TIME_ANALYSE (0xD0BF0000ul | HDTOUT_COMMAND)
#define HDTOUT_BREAKPOINT (0xB0BF0000ul | HDTOUT_COMMAND)
#define HDTOUT_ERROR (0x1EBF0000ul | HDTOUT_COMMAND)
#define HDTOUT_ERROR_HEAP_ALLOCATION 0x1
#define HDTOUT_ERROR_HEAP_AllOCATE_FAIL 0x2
#define HDTOUT_PRINTCTRL_OFF 0
#define HDTOUT_PRINTCTRL_ON 1
#define HDTOUT_ALL_CORES 0
#define HDTOUT_BSP_ONLY 1
#define HDTOUT_BUFFER_MODE_OFF 0
#define HDTOUT_BUFFER_MODE_ON 1
#define HDTOUT_HEADER_SIGNATURE 0xDB1099CCul
#define HDTOUT_DEFAULT_BUFFER_SIZE 0x1000
/// HDTOUT Header.
typedef struct _HDTOUT_HEADER {
UINT32 Signature; ///< 0xDB1099CC
UINT16 Version; ///< HDTOUT version.
UINT16 BufferSize; ///< Size in bytes.
UINT16 DataIndex; ///< Data Index.
UINT8 PrintCtrl; ///< 0 off no print 1 on print
UINT8 NumBreakpointUnit; ///< default 0 no bp unit others number of bp unit
UINT32 FuncListAddr; ///< 32 bit address to the list of functions that script can execute
UINT8 ConsoleType; ///< Console type - deprecated
UINT8 Event; ///< Event type. - deprecated
UINT8 OutBufferMode; ///< Off:stack mode, On: heap mode - deprecated
UINT32 EnableMask; ///< Bitmap to select which part should be streamed out
UINT64 ConsoleFilter; ///< Filter use to select which part should be streamed out
UINT8 BspOnlyFlag; ///< 1 Only Enable Bsp output, 0 enable On All cores
UINT8 Reserved[56 - 32]; ///< Reserved for header expansion
CHAR8 BreakpointList[300]; ///< Breakpoint list
CHAR8 StatusStr[156]; ///< Shows current node, DCT, CS,...
CHAR8 Data[2]; ///< HDTOUT content. Its size will be determined by BufferSize.
} HDTOUT_HEADER;
#define IDS_HDTOUT_BP_AND_OFF 0
#define IDS_HDTOUT_BP_AND_ON 1
#define IDS_HDTOUT_BPFLAG_FORMAT_STR 0
#define IDS_HDTOUT_BPFLAG_STATUS_STR 1
#define HDTOUT_BP_ACTION_HALT 1
#define HDTOUT_BP_ACTION_PRINTON 2
#define HDTOUT_BP_ACTION_PRINTONE 3
#define HDTOUT_BP_ACTION_PRINTOFF 4
///breakpoint unit of HDTOUT
typedef struct _BREAKPOINT_UNIT {
UINT8 AndFlag : 1; ///< Next string is ANDed to current string
UINT8 BpFlag : 1; ///< Format string or Status string
UINT8 Action : 4; ///< Halt, start HDTOUT, or stop HDT,...
UINT8 BpStrOffset; ///< Offset from BreakpointList to the breakpoint string
} BREAKPOINT_UNIT;
BOOLEAN
AmdIdsHdtOutSupport (
VOID
);
#endif //_IDS_HDTOUT_H_

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src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpRam.h
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@ -1,73 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Integrated Debug Print Routines
*
* Contains all functions related to IDS Debug Print
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_DP_RAM_H_
#define _IDS_DP_RAM_H_
#pragma pack (push, 1)
///Debug Print RAM signature
#define DEBUG_PRINT_RAM_SIG MAKE_SIGNATURE ('D','P','R','M')
/// Debug Print Ram Header
typedef struct _IDS_DEBUG_PRINT_RAM_HEADER {
SIGNATURE DpRamSig; /// 00 'D','P','R','M'
UINT32 LatestIdx; /// 04 Latest Index
UINT8 Reserved[8]; /// Reserved
} IDS_DEBUG_PRINT_RAM_HEADER;
///Debug Print RAM Signature Offset
#define DEBUG_PRINT_RAM_SIG_ADDR ((UINTN) IDS_DPRAM_BASE + (UINTN) &(((IDS_DEBUG_PRINT_RAM_HEADER *) 0)->DpRamSig))
///Debug Print RAM Latest Index Offset
#define DEBUG_PRINT_RAM_LATESTIDX_ADDR ((UINTN) IDS_DPRAM_BASE + (UINTN) &(((IDS_DEBUG_PRINT_RAM_HEADER *) 0)->LatestIdx))
///Print Buffer start
#define DEBUG_PRINT_BUFFER_START ((UINTN) IDS_DPRAM_BASE + sizeof (IDS_DEBUG_PRINT_RAM_HEADER))
///Print Buffer Size
#define DEBUG_PRINT_BUFFER_SIZE ((UINT32) IDS_DPRAM_SIZE - sizeof (IDS_DEBUG_PRINT_RAM_HEADER))
///Debug Print RAM default Value
#define DEBUG_PRINT_BUFFER_DFT_VALUE ((UINT8) 0xCC)
#pragma pack (pop)
#endif //_IDS_DP_RAM_H_

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src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/IdsF15AllService.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA IDS Translation
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_F15_ALLSERVICE_H_
#define _IDS_F15_ALLSERVICE_H_
#ifdef __IDS_EXTENDED__
#include IDS_EXT_INCLUDE_F15 (IdsIntF15AllService)
#endif
#endif

49
src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA IDS Translation
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_F15_KV_ALLSERVICE_H_
#define _IDS_F15_KV_ALLSERVICE_H_
#ifdef __IDS_EXTENDED__
#include IDS_EXT_INCLUDE_F15_KV (IdsIntF15KvAllService)
#endif
#endif //_IDS_F15_KV_ALLSERVICE_H_

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src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h
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/* $NoKeywords:$ */
/**
* @file
*
* IDS NV definition for F15Kv
*
* Auto generated from CBS XML file
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS F15Kv
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDSF15KVNVDEF_H_
#define _IDSF15KVNVDEF_H_
///HTC Enable
///Enable or disable Hardware Thermal Control. D18F3x64[0]
typedef enum {
IdsNvThermalHTCEnDisabled = 0,///<Disabled
IdsNvThermalHTCEnEnabled = 1,///<Enabled
IdsNvThermalHTCEnAuto = 3,///<Auto
} IdsNvThermalHTCEn;
///HTC Override
///Enable or disable Thermal Control Override
typedef enum {
IdsNvThermalHTCOverrideDisabled = 0,///<Disabled
IdsNvThermalHTCOverrideEnabled = 1,///<Enabled
} IdsNvThermalHTCOverride;
///HTC P-state limit select
///Specifies the P-state limit of all cores when in the P-state based HTC-active state
#define IdsNvThermalHtcPstateLimitMin 0
#define IdsNvThermalHtcPstateLimitMax 7
///HTC Temperature Hysteresis
///Sets the temperature hysteresis for HTC. D18F3x64[27:24]
#define IdsNvThermalHTCTempHysMin 0
#define IdsNvThermalHTCTempHysMax 0xF
///HTC Activation Temp
///Sets the HTC temperature limit. D18F3x64[22:16]
#define IdsNvThermalHTCActTempMin 0
#define IdsNvThermalHTCActTempMax 0x7F
///Bank Interleave
///Interleave memory blocks across the DRAM chip selects for node 0.
typedef enum {
IdsNvMemMappingBankInterleaveDisabled = 0,///<Disabled
IdsNvMemMappingBankInterleaveAuto = 1,///<Auto
} IdsNvMemMappingBankInterleave;
///DRAM Channel Interleave
///Interleave between two DCTs when they are in unganged mode.
typedef enum {
IdsNvMemMappingChlInterleaveAddress_bit_6 = 0,///<Address bit 6
IdsNvMemMappingChlInterleaveAddress_bit_12 = 1,///<Address bit 12
IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_ = 2,///<Hash: exclusive OR of address bits[20:16, 6]
IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_ = 3,///<Hash: excluseive OR of address bits[20:16, 9]
IdsNvMemMappingChlInterleaveAddress_bit_8 = 4,///<Address bit 8
IdsNvMemMappingChlInterleaveAddress_bit_9 = 5,///<Address bit 9
IdsNvMemMappingChlInterleaveDisabled = 0xF,///<Disabled
IdsNvMemMappingChlInterleaveAuto = 0xFF,///<Auto
} IdsNvMemMappingChlInterleave;
///ECC Symbol Size
///ECC symbol size and code selection. D18F3x180[25]
typedef enum {
IdsNvEccSymbolSizex4 = 0,///<x4
IdsNvEccSymbolSizex8 = 1,///<x8
IdsNvEccSymbolSizeAuto = 3,///<Auto
} IdsNvEccSymbolSize;
///DRAM prefetches triggered from CPU requests
///Enable or disable DRAM prefetches Prefetch triggered by CPU requests.
typedef enum {
IdsNvPrefetchPrefCpuDis0 = 0,///<0
IdsNvPrefetchPrefCpuDis1 = 1,///<1
IdsNvPrefetchPrefCpuDisAuto = 3,///<Auto
} IdsNvPrefetchPrefCpuDis;
///HW prefetch training on SW Prefetches
///Enable or disable Hardware Prefetch training on Software Prefetches
typedef enum {
IdsNvPrefetchDisHWPFforSWPF0 = 0,///<0
IdsNvPrefetchDisHWPFforSWPF1 = 1,///<1
IdsNvPrefetchDisHWPFforSWPFAuto = 3,///<Auto
} IdsNvPrefetchDisHWPFforSWPF;
///Hardware Prefetches
///Enable or disable Hardware Prefetches.
typedef enum {
IdsNvPrefetchDisHWPF0 = 0,///<0
IdsNvPrefetchDisHWPF1 = 1,///<1
IdsNvPrefetchDisHWPFAuto = 3,///<Auto
} IdsNvPrefetchDisHWPF;
///UMI Gen2
///Enable or disable UMI link Gen2
typedef enum {
IdsNvFchGppUmiGen2Disabled = 0,///<Disabled
IdsNvFchGppUmiGen2Enabled = 1,///<Enabled
} IdsNvFchGppUmiGen2;
///SATA Controller
///Disable or enable OnChip SATA controller
typedef enum {
IdsNvFchSataEnableDisabled = 0,///<Disabled
IdsNvFchSataEnableEnabled = 1,///<Enabled
} IdsNvFchSataEnable;
///SATA Mode
///Select OnChip SATA Type
typedef enum {
IdsNvFchSataClassNative_IDE = 0,///<Native IDE
IdsNvFchSataClassRAID = 1,///<RAID
IdsNvFchSataClassAHCI = 3,///<AHCI
IdsNvFchSataClassLegacy_IDE = 3,///<Legacy IDE
IdsNvFchSataClassIDE__AHCI = 4,///<IDE->AHCI
IdsNvFchSataClassAHCI_as_ID_0x7804 = 5,///<AHCI as ID 0x7804
IdsNvFchSataClassIDE__AHCI_as_ID_0x7804 = 6,///<IDE->AHCI as ID 0x7804
} IdsNvFchSataClass;
///OnChip IDE
///Select OnChip IDE controller mode
typedef enum {
IdsNvFchSataIdeModeLegacy_IDE = 0,///<Legacy IDE
IdsNvFchSataIdeModeNative_IDE = 1,///<Native IDE
} IdsNvFchSataIdeMode;
///IDE Controller
///Disable or enable OnChip IDE controller
typedef enum {
IdsNvFchSataIdeEnableDisabled = 0,///<Disabled
IdsNvFchSataIdeEnableEnabled = 1,///<Enabled
} IdsNvFchSataIdeEnable;
///XHC Switch (Bus 0 Dev 16 Fn 0/1)
///Select disable or enable XHCI HCs (Bus 0 Dev 16 Fn 0/1)
typedef enum {
IdsNvFchUsbXhciSwitchDisabled = 0,///<Disabled
IdsNvFchUsbXhciSwitchEnabled = 1,///<Enabled
} IdsNvFchUsbXhciSwitch;
///USB1(Bus 0 Dev 18 Fn 0/2)
///Select disable or enable USB1 HCs (Bus 0 Dev 18 Fn 0/2)
typedef enum {
IdsNvFchUsbOhci1EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci1EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci1Enable;
///USB2 (Bus 0 Dev 19 Fn 0/2)
///Select disable or enable USB2 HCs (Bus 0 Dev 19 Fn 0/2)
typedef enum {
IdsNvFchUsbOhci2EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci2EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci2Enable;
///USB3 (Bus 0 Dev 22 Fn 0/2)
///Select disable or enable USB3 HCs (Bus 0 Dev 22 Fn 0/2)
typedef enum {
IdsNvFchUsbOhci3EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci3EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci3Enable;
///USB4 (Bus 0 Dev 20 Fn 5)
///Select disable or enable USB4 HC (Bus 0 Dev 20 Fn 5)
typedef enum {
IdsNvFchUsbOhci4EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci4EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci4Enable;
///Hardware Monitor Enable
///Master switch to enable or disable hardware monitor function
typedef enum {
IdsNvFchHwmEnableDisabled = 0,///<Disabled
IdsNvFchHwmEnableEnabled = 1,///<Enabled
} IdsNvFchHwmEnable;
///In-Chip IR
///Enable or disable the In-Chip IR
typedef enum {
IdsNvFchIrConfigDisabled = 0,///<Disabled
IdsNvFchIrConfigRX_TX0_Only = 1,///<RX_TX0 Only
IdsNvFchIrConfigRX_TX1_Only = 2,///<RX_TX1 Only
IdsNvFchIrConfigRX__TX0__and_TX1 = 3,///<RX, TX0, and TX1
} IdsNvFchIrConfig;
///SD Configuration Mode
///Select SD Mode
typedef enum {
IdsNvFchSdConfigDisabled = 0,///<Disabled
IdsNvFchSdConfigADMA = 1,///<ADMA
IdsNvFchSdConfigDMA = 2,///<DMA
IdsNvFchSdConfigPIO = 3,///<PIO
} IdsNvFchSdConfig;
///Azalia Device
///Select disable or enable Azalia Device
typedef enum {
IdsNvFchAzaliaControlAuto = 0,///<Auto
IdsNvFchAzaliaControlDisabled = 1,///<Disabled
IdsNvFchAzaliaControlEnabled = 2,///<Enabled
IdsNvFchAzaliaControlReserved = 3,///<Reserved
} IdsNvFchAzaliaControl;
///Integrated Graphics Controller
///Enable Integrate Graphics controller
typedef enum {
IdsNvGnbGfxiGPU_CONTROLAuto = 0,///<Auto
IdsNvGnbGfxiGPU_CONTROLDisabled = 1,///<Disabled
IdsNvGnbGfxiGPU_CONTROLForces = 2,///<Forces
} IdsNvGnbGfxiGPU_CONTROL;
///UMA Frame buffer Size
///Set UMA FB size
typedef enum {
IdsNvGnbGfxUmaFrameBufferSizeAuto = 0,///<Auto
IdsNvGnbGfxUmaFrameBufferSize32M = 1,///<32M
IdsNvGnbGfxUmaFrameBufferSize64M = 2,///<64M
IdsNvGnbGfxUmaFrameBufferSize128M = 3,///<128M
IdsNvGnbGfxUmaFrameBufferSize256M = 4,///<256M
IdsNvGnbGfxUmaFrameBufferSize384M = 5,///<384M
IdsNvGnbGfxUmaFrameBufferSize512M = 6,///<512M
IdsNvGnbGfxUmaFrameBufferSize1G = 7,///<1G
IdsNvGnbGfxUmaFrameBufferSize2G = 8,///<2G
IdsNvGnbGfxUmaFrameBufferSize4G = 9,///<4G
} IdsNvGnbGfxUmaFrameBufferSize;
///NB Azalia
///Enable Integrate HD Audio controller
typedef enum {
IdsNvGnbGfxNbAzaliaDisabled = 0,///<Disabled
IdsNvGnbGfxNbAzaliaEnabled = 1,///<Enabled
IdsNvGnbGfxNbAzaliaAuto = 0xf,///<Auto
} IdsNvGnbGfxNbAzalia;
///PSPP Policy
///PCIe speed power policy
typedef enum {
IdsNvGnbPciePsppPolicyDisabled = 0,///<Disabled
IdsNvGnbPciePsppPolicyPerformance = 1,///<Performance
IdsNvGnbPciePsppPolicyBalanced_High = 2,///<Balanced-High
IdsNvGnbPciePsppPolicyBalanced_Low = 3,///<Balanced-Low
IdsNvGnbPciePsppPolicyPower_Saving = 4,///<Power Saving
IdsNvGnbPciePsppPolicyAuto = 5,///<Auto
} IdsNvGnbPciePsppPolicy;
///IOMMU
///
typedef enum {
IdsNvGnbNbIOMMUDisabled = 0,///<Disabled
IdsNvGnbNbIOMMUEnabled = 1,///<Enabled
} IdsNvGnbNbIOMMU;
#endif // _IDSF15KVNVDEF_H_

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src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA IDS Translation
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_F15_TN_ALLSERVICE_H_
#define _IDS_F15_TN_ALLSERVICE_H_
#ifdef __IDS_EXTENDED__
#include IDS_EXT_INCLUDE_F15_TN (IdsIntF15TnAllService)
#endif
#endif //_IDS_F15_TN_ALLSERVICE_H_

287
src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
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/* $NoKeywords:$ */
/**
* @file
*
* IDS NV definition for F15Tn
*
* Auto generated from CBS XML file
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS F15Tn
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDSF15TNNVDEF_H_
#define _IDSF15TNNVDEF_H_
///HTC Enable
///Enable or disable Hardware Thermal Control. D18F3x64[0]
typedef enum {
IdsNvThermalHTCEnDisabled = 0,///<Disabled
IdsNvThermalHTCEnEnabled = 1,///<Enabled
IdsNvThermalHTCEnAuto = 3,///<Auto
} IdsNvThermalHTCEn;
///HTC Override
///Enable or disable Thermal Control Override
typedef enum {
IdsNvThermalHTCOverrideDisabled = 0,///<Disabled
IdsNvThermalHTCOverrideEnabled = 1,///<Enabled
} IdsNvThermalHTCOverride;
///HTC P-state limit select
///Specifies the P-state limit of all cores when in the P-state based HTC-active state
#define IdsNvThermalHtcPstateLimitMin 0
#define IdsNvThermalHtcPstateLimitMax 7
///HTC Temperature Hysteresis
///Sets the temperature hysteresis for HTC. D18F3x64[27:24]
#define IdsNvThermalHTCTempHysMin 0
#define IdsNvThermalHTCTempHysMax 0xF
///HTC Activation Temp
///Sets the HTC temperature limit. D18F3x64[22:16]
#define IdsNvThermalHTCActTempMin 0
#define IdsNvThermalHTCActTempMax 0x7F
///Bank Interleave
///Interleave memory blocks across the DRAM chip selects for node 0.
typedef enum {
IdsNvMemMappingBankInterleaveDisabled = 0,///<Disabled
IdsNvMemMappingBankInterleaveAuto = 1,///<Auto
} IdsNvMemMappingBankInterleave;
///DRAM Channel Interleave
///Interleave between two DCTs when they are in unganged mode.
typedef enum {
IdsNvMemMappingChlInterleaveAddress_bit_6 = 0,///<Address bit 6
IdsNvMemMappingChlInterleaveAddress_bit_12 = 1,///<Address bit 12
IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_ = 2,///<Hash: exclusive OR of address bits[20:16, 6]
IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_ = 3,///<Hash: excluseive OR of address bits[20:16, 9]
IdsNvMemMappingChlInterleaveAddress_bit_8 = 4,///<Address bit 8
IdsNvMemMappingChlInterleaveAddress_bit_9 = 5,///<Address bit 9
IdsNvMemMappingChlInterleaveDisabled = 0xF,///<Disabled
IdsNvMemMappingChlInterleaveAuto = 0xFF,///<Auto
} IdsNvMemMappingChlInterleave;
///ECC Symbol Size
///ECC symbol size and code selection. D18F3x180[25]
typedef enum {
IdsNvEccSymbolSizex4 = 0,///<x4
IdsNvEccSymbolSizex8 = 1,///<x8
IdsNvEccSymbolSizeAuto = 3,///<Auto
} IdsNvEccSymbolSize;
///DRAM prefetches triggered from CPU requests
///Enable or disable DRAM prefetches Prefetch triggered by CPU requests.
typedef enum {
IdsNvPrefetchPrefCpuDis0 = 0,///<0
IdsNvPrefetchPrefCpuDis1 = 1,///<1
IdsNvPrefetchPrefCpuDisAuto = 3,///<Auto
} IdsNvPrefetchPrefCpuDis;
///HW prefetch training on SW Prefetches
///Enable or disable Hardware Prefetch training on Software Prefetches
typedef enum {
IdsNvPrefetchDisHWPFforSWPF0 = 0,///<0
IdsNvPrefetchDisHWPFforSWPF1 = 1,///<1
IdsNvPrefetchDisHWPFforSWPFAuto = 3,///<Auto
} IdsNvPrefetchDisHWPFforSWPF;
///Hardware Prefetches
///Enable or disable Hardware Prefetches.
typedef enum {
IdsNvPrefetchDisHWPF0 = 0,///<0
IdsNvPrefetchDisHWPF1 = 1,///<1
IdsNvPrefetchDisHWPFAuto = 3,///<Auto
} IdsNvPrefetchDisHWPF;
///UMI Gen2
///Enable or disable UMI link Gen2
typedef enum {
IdsNvFchGppUmiGen2Disabled = 0,///<Disabled
IdsNvFchGppUmiGen2Enabled = 1,///<Enabled
} IdsNvFchGppUmiGen2;
///SATA Controller
///Disable or enable OnChip SATA controller
typedef enum {
IdsNvFchSataEnableDisabled = 0,///<Disabled
IdsNvFchSataEnableEnabled = 1,///<Enabled
} IdsNvFchSataEnable;
///SATA Mode
///Select OnChip SATA Type
typedef enum {
IdsNvFchSataClassNative_IDE = 0,///<Native IDE
IdsNvFchSataClassRAID = 1,///<RAID
IdsNvFchSataClassAHCI = 3,///<AHCI
IdsNvFchSataClassLegacy_IDE = 3,///<Legacy IDE
IdsNvFchSataClassIDE__AHCI = 4,///<IDE->AHCI
IdsNvFchSataClassAHCI_as_ID_0x7804 = 5,///<AHCI as ID 0x7804
IdsNvFchSataClassIDE__AHCI_as_ID_0x7804 = 6,///<IDE->AHCI as ID 0x7804
} IdsNvFchSataClass;
///OnChip IDE
///Select OnChip IDE controller mode
typedef enum {
IdsNvFchSataIdeModeLegacy_IDE = 0,///<Legacy IDE
IdsNvFchSataIdeModeNative_IDE = 1,///<Native IDE
} IdsNvFchSataIdeMode;
///IDE Controller
///Disable or enable OnChip IDE controller
typedef enum {
IdsNvFchSataIdeEnableDisabled = 0,///<Disabled
IdsNvFchSataIdeEnableEnabled = 1,///<Enabled
} IdsNvFchSataIdeEnable;
///XHC Switch (Bus 0 Dev 16 Fn 0/1)
///Select disable or enable XHCI HCs (Bus 0 Dev 16 Fn 0/1)
typedef enum {
IdsNvFchUsbXhciSwitchDisabled = 0,///<Disabled
IdsNvFchUsbXhciSwitchEnabled = 1,///<Enabled
} IdsNvFchUsbXhciSwitch;
///USB1(Bus 0 Dev 18 Fn 0/2)
///Select disable or enable USB1 HCs (Bus 0 Dev 18 Fn 0/2)
typedef enum {
IdsNvFchUsbOhci1EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci1EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci1Enable;
///USB2 (Bus 0 Dev 19 Fn 0/2)
///Select disable or enable USB2 HCs (Bus 0 Dev 19 Fn 0/2)
typedef enum {
IdsNvFchUsbOhci2EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci2EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci2Enable;
///USB3 (Bus 0 Dev 22 Fn 0/2)
///Select disable or enable USB3 HCs (Bus 0 Dev 22 Fn 0/2)
typedef enum {
IdsNvFchUsbOhci3EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci3EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci3Enable;
///USB4 (Bus 0 Dev 20 Fn 5)
///Select disable or enable USB4 HC (Bus 0 Dev 20 Fn 5)
typedef enum {
IdsNvFchUsbOhci4EnableDisabled = 0,///<Disabled
IdsNvFchUsbOhci4EnableEnabled = 1,///<Enabled
} IdsNvFchUsbOhci4Enable;
///Hardware Monitor Enable
///Master switch to enable or disable hardware monitor function
typedef enum {
IdsNvFchHwmEnableDisabled = 0,///<Disabled
IdsNvFchHwmEnableEnabled = 1,///<Enabled
} IdsNvFchHwmEnable;
///In-Chip IR
///Enable or disable the In-Chip IR
typedef enum {
IdsNvFchIrConfigDisabled = 0,///<Disabled
IdsNvFchIrConfigRX_TX0_Only = 1,///<RX_TX0 Only
IdsNvFchIrConfigRX_TX1_Only = 2,///<RX_TX1 Only
IdsNvFchIrConfigRX__TX0__and_TX1 = 3,///<RX, TX0, and TX1
} IdsNvFchIrConfig;
///SD Configuration Mode
///Select SD Mode
typedef enum {
IdsNvFchSdConfigDisabled = 0,///<Disabled
IdsNvFchSdConfigADMA = 1,///<ADMA
IdsNvFchSdConfigDMA = 2,///<DMA
IdsNvFchSdConfigPIO = 3,///<PIO
} IdsNvFchSdConfig;
///Azalia Device
///Select disable or enable Azalia Device
typedef enum {
IdsNvFchAzaliaControlAuto = 0,///<Auto
IdsNvFchAzaliaControlDisabled = 1,///<Disabled
IdsNvFchAzaliaControlEnabled = 2,///<Enabled
IdsNvFchAzaliaControlReserved = 3,///<Reserved
} IdsNvFchAzaliaControl;
///Integrated Graphics Controller
///Enable Integrate Graphics controller
typedef enum {
IdsNvGnbGfxiGPU_CONTROLAuto = 0,///<Auto
IdsNvGnbGfxiGPU_CONTROLDisabled = 1,///<Disabled
IdsNvGnbGfxiGPU_CONTROLForces = 2,///<Forces
} IdsNvGnbGfxiGPU_CONTROL;
///UMA Frame buffer Size
///Set UMA FB size
typedef enum {
IdsNvGnbGfxUmaFrameBufferSizeAuto = 0,///<Auto
IdsNvGnbGfxUmaFrameBufferSize32M = 1,///<32M
IdsNvGnbGfxUmaFrameBufferSize64M = 2,///<64M
IdsNvGnbGfxUmaFrameBufferSize128M = 3,///<128M
IdsNvGnbGfxUmaFrameBufferSize256M = 4,///<256M
IdsNvGnbGfxUmaFrameBufferSize384M = 5,///<384M
IdsNvGnbGfxUmaFrameBufferSize512M = 6,///<512M
IdsNvGnbGfxUmaFrameBufferSize1G = 7,///<1G
IdsNvGnbGfxUmaFrameBufferSize2G = 8,///<2G
IdsNvGnbGfxUmaFrameBufferSize4G = 9,///<4G
} IdsNvGnbGfxUmaFrameBufferSize;
///NB Azalia
///Enable Integrate HD Audio controller
typedef enum {
IdsNvGnbGfxNbAzaliaDisabled = 0,///<Disabled
IdsNvGnbGfxNbAzaliaEnabled = 1,///<Enabled
IdsNvGnbGfxNbAzaliaAuto = 0xf,///<Auto
} IdsNvGnbGfxNbAzalia;
///PSPP Policy
///PCIe speed power policy
typedef enum {
IdsNvGnbPciePsppPolicyDisabled = 0,///<Disabled
IdsNvGnbPciePsppPolicyPerformance = 1,///<Performance
IdsNvGnbPciePsppPolicyBalanced_High = 2,///<Balanced-High
IdsNvGnbPciePsppPolicyBalanced_Low = 3,///<Balanced-Low
IdsNvGnbPciePsppPolicyPower_Saving = 4,///<Power Saving
IdsNvGnbPciePsppPolicyAuto = 5,///<Auto
} IdsNvGnbPciePsppPolicy;
///IOMMU
///
typedef enum {
IdsNvGnbNbIOMMUDisabled = 0,///<Disabled
IdsNvGnbNbIOMMUEnabled = 1,///<Enabled
} IdsNvGnbNbIOMMU;
#endif // _IDSF15TNNVDEF_H_

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src/vendorcode/amd/pi/00630F01/Proc/IDS/IdsLib.h
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@ -1,381 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA Integrated Debug Macros
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_LIB_H_
#define _IDS_LIB_H_
#include "OptionsIds.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "Table.h"
///Specific time stamp performance analysis which need ids control support
#if IDSOPT_CONTROL_ENABLED == TRUE
#define PERF_SPEC_TS_ANALYSE(StdHeader) IdsPerfSpecTsAnalyse(StdHeader)
#else
#define PERF_SPEC_TS_ANALYSE(StdHeader)
#endif
#define IDS_NV_READ(NvValue, Nvid, IdsNvPtr, StdHeader)\
NvValue = AmdIdsNvReader ((Nvid), (IdsNvPtr), (StdHeader));
#define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader)\
if (((NvValue) = AmdIdsNvReader ((Nvid), (IdsNvPtr), (StdHeader))) != IDS_UNSUPPORTED)
#define IDS_GET_MASK32(HighBit, LowBit) ((((UINT32) 1 << (HighBit - LowBit + 1)) - 1) << LowBit)
#define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap.
///Macro for Ids family feat
#define MAKE_IDS_FAMILY_FEAT_ALL_CORES(FEAT_ID, FAMILY, FUNCTION) \
{IDS_FEAT_COMMON, IDS_ALL_CORES, FEAT_ID, FAMILY, FUNCTION}
///Macro for signature
#define MAKE_SIGNATURE(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a))
typedef UINT32 SIGNATURE;
// TYPEDEFS, STRUCTURES, ENUMS
//
typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader);
///Structure define for IdsAgesaRunFcnOnApLate
typedef struct _IDSAPLATETASK {
PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do
VOID *ApTaskPara; ///< Point to Ap function parameter1
} IDSAPLATETASK;
/// Data Structure defining IDS Data in HEAP
/// This data structure contains information that is stored in HEAP and will be
/// used in IDS backend function. It includes the size of memory to be allocated
/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA
/// table and the register table to override mem setting. It also includes a base
/// address of IDS override image which will be used to control the behavior of
/// AGESA testpoint if this feature is enabled.
typedef struct {
BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset
UINT64 IdsImageBase; ///< IDS Override Image Base Address
UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap
UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table
UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table
UINT32 IdsExtendOffset; ///< Offset of Ids extend heap
} IDS_CONTROL_STRUCT;
/// Data Structure of Parameters for TestPoint_TSC.
typedef struct {
UINT32 LineInFile; ///< Line of current time counter
UINT64 Description; ///<Description ID
UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC
} TestPoint_TSC;
#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY)
/// Data Structure of Parameters for TP_Perf_STRUCT.
typedef struct {
UINT32 Signature; ///< "PERF"
UINT32 Version; ///< version
UINT32 Index; ///< The Index of TP_Perf_STRUCT
UINT32 TscInMhz; ///< Tsc counter in 1 mhz
TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT
} TP_Perf_STRUCT;
///Bus speed Optimization
typedef enum {
IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance
IDS_POWER_POLICY_POWER = 1, ///< Power
IDS_POWER_POLICY_AUTO = 3, ///< Auto
} IDS_NV_AMDBUSSPEEDOPTIMIZATION;
///IDS early AP task
typedef struct _IDS_EARLY_AP_TASK0 {
UINT8 Core; ///< Core to run Aptask
AP_TASK ApTask; ///< Speicify task property
} IDS_EARLY_AP_TASK0;
#define IDS_EARLY_AP_TASK_PARA_NUM 100
///IDS early AP task
typedef struct _IDS_EARLY_AP_TASK {
IDS_EARLY_AP_TASK0 Ap_Task0; ///< Ap Task exclude parameter buffer
UINT8 Parameters[IDS_EARLY_AP_TASK_PARA_NUM]; ///< Parameter buffer
} IDS_EARLY_AP_TASK;
///AP service Time Point
typedef enum {
IDS_AP_RUN_CODE_EARLY, ///< Amdinitearly
IDS_AP_RUN_CODE_POST, ///< Amdinitpost
IDS_AP_RUN_CODE_LATE, ///< After AmdInitPost
IDS_AP_RUN_CODE_END ///< Last element
} IDS_AP_RUN_CODE_TIMEPOINT;
/// Parameters for IdsRunCodeOnCores
typedef struct _IDS_RUNCODE_PARAMS {
IDS_AP_RUN_CODE_TIMEPOINT TimePoint; ///< TimePoint
UINT8 Socket; ///< IDS_ALL_SOCKET: all sockets
UINT8 Core; ///< IDS_ALL_CORE: all cores
PF_AP_TASK_IO ApTask; ///< Only support this type function
UINT16 ParamsDataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword
VOID *ParamsDataPtr; ///< Pointer to the parameter
} IDS_RUNCODE_PARAMS;
#define IDS_ALL_SOCKET 0xFF
#define IDS_ALL_MODULE 0xFF
#define IDS_ALL_CORE 0xFF
#define IDS_ALL_DCT 0xFF
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
IDS_STATUS
IdsSubUCode (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
IDS_STATUS
IdsSubGangingMode (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
IDS_STATUS
IdsSubPowerDownMode (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
IDS_STATUS
IdsSubAllMemClkEn (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
IDS_STATUS
IdsSubPostPState (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
IDS_STATUS
IdsSubPowerPolicyOverride (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
AGESA_STATUS
AmdIdsCtrlInitialize (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
IDS_STATUS
AmdIdsNvReader (
IN UINT16 IdsNvId,
IN IDS_NV_ITEM *NvTablePtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
AmdGetIdsNvTable (
IN OUT VOID **IdsNvTable,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsOutPort (
IN UINT32 Addr,
IN UINT32 Value,
IN UINT32 Flag
);
IDS_STATUS
IdsCommonReturn (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
AGESA_STATUS
IdsAgesaRunFcnOnApLate (
IN UINTN ApicIdOfCore,
IN IDSAPLATETASK *ApLateTaskPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsRunCodeOnCores (
IN IDS_RUNCODE_PARAMS *PIdsRuncodeParams,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
IdsAgesaRunFcnOnAllCoresLate (
IN IDSAPLATETASK *ApLateTaskPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
IDS_STATUS
IdsParseFeatTbl (
IN AGESA_IDS_OPTION IdsOption,
IN CONST IDS_FAMILY_FEAT_STRUCT * PIdsFeatTbl[],
IN OUT VOID *DataPtr,
IN IDS_NV_ITEM *IdsNvPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
IDS_STATUS
IdsSubPowerDownCtrl (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
IDS_STATUS
IdsSubHdtOut (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
UINT8
IdsGetNumPstatesFamCommon (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsApRunCodeOnAllLocalCores (
IN AP_TASK *TaskPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
IDS_STATUS
IdsSubTargetPstate (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
VOID
IdsMakePciRegEntry (
IN OUT TABLE_ENTRY_FIELDS **TableEntry,
IN UINT64 Family,
IN UINT64 Revision,
IN UINT32 PciAddr,
IN UINT32 Data,
IN UINT32 Mask
);
VOID
IdsLibPciWriteBitsToAllNode (
IN PCI_ADDR PciAddress,
IN UINT8 Highbit,
IN UINT8 Lowbit,
IN UINT32 *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsRunCodeOnCoreEarly (
IN UINT8 Socket,
IN UINT8 Core,
IN AP_TASK* ApTask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsGetMask64bits (
IN UINT64 RegVal,
IN UINT8 Highbit,
IN UINT8 Lowbit,
IN OUT UINT64 *AndMask,
IN OUT UINT64 *OrMask
);
VOID
IdsGetMask32bits (
IN UINT32 RegVal,
IN UINT8 Highbit,
IN UINT8 Lowbit,
IN OUT UINT32 *AndMask,
IN OUT UINT32 *OrMask
);
VOID
IdsGetMask16bits (
IN UINT16 RegVal,
IN UINT8 Highbit,
IN UINT8 Lowbit,
IN OUT UINT32 *AndMask,
IN OUT UINT32 *OrMask
);
VOID
IdsGetStartEndModule (
IN UINT8 ModuleId,
IN OUT UINT8 *StartModule,
IN OUT UINT8 *EndModule
);
VOID
IdsGetStartEndSocket (
IN UINT8 SocketId,
IN OUT UINT8 *StartSocket,
IN OUT UINT8 *EndSocket
);
BOOLEAN
IdsCheckPciExist (
IN PCI_ADDR PciAddr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
IdsLibDataMaskSet32 (
IN OUT UINT32 *Value,
IN UINT32 AndMask,
IN UINT32 OrMask
);
#define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFFul
#endif //_IDS_LIB_H_

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src/vendorcode/amd/pi/00630F01/Proc/IDS/OptionsIds.h
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/* $NoKeywords:$ */
/**
* @file
*
* IDS Option File
*
* This file is used to switch on/off IDS features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_IDS_H_
#define _OPTION_IDS_H_
/**
*
* This file generates the defaults tables for the Integrated Debug Support
* Module. The documented build options are imported from a user controlled
* file for processing. The build options for the Integrated Debug Support
* Module are listed below:
*
* IDSOPT_IDS_ENABLED
* IDSOPT_ERROR_TRAP_ENABLED
* IDSOPT_CONTROL_ENABLED
*
* Warning: When you enable the IDSOPT_CONTROL_NV_TO_CMOS feature.
* please make the cmos region defined by IDS_OPT_CMOS_REGION_START &
* IDS_OPT_CMOS_REGION_END can be touched between IDS HOOK point
* IDS_CPU_Early_Override and IDS_BEFORE_AP_EARLY_HALT of BSP
*
* IDSOPT_CONTROL_NV_TO_CMOS
* IDS_OPT_CMOS_INDEX_PORT
* IDS_OPT_CMOS_DATA_PORT
* IDS_OPT_CMOS_REGION_START
* IDS_OPT_CMOS_REGION_END
*
* IDSOPT_TRACING_ENABLED
* IDSOPT_TRACING_CONSOLE_HDTOUT
* IDSOPT_TRACING_CONSOLE_SERIALPORT
* IDSOPT_SERIAL_PORT (default 0x3F8)
* IDSOPT_TRACING_CONSOLE_REDIRECT_IO
* IDSOPT_DEBUG_PRINT_IO_PORT (default 0x80)
* IDSOPT_TRACING_CONSOLE_RAM
* IDSOPT_DPRAM_BASE
* IDSOPT_DPRAM_SIZE
* IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL (default FALSE)
* IDSOPT_CUSTOMIZE_TRACING_SERVICE
* IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
* IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
*
* IDSOPT_TRACE_BLD_CFG
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
* IDSOPT_DEBUG_CODE_ENABLED
* IDSOPT_IDT_EXCEPTION_TRAP
* IDSOPT_C_OPTIMIZATION_DISABLED
*
**/
#endif

1593
src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
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File diff suppressed because it is too large Load Diff

4
src/vendorcode/amd/pi/Kconfig
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@ -26,11 +26,10 @@
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || SOC_AMD_STONEYRIDGE
if CPU_AMD_PI_00730F01 || SOC_AMD_STONEYRIDGE
config AGESA_BINARY_PI_VENDORCODE_PATH
string "AGESA PI directory path"
default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01
default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01
default "src/vendorcode/amd/pi/00670F00" if AMD_APU_MERLINFALCON
default "src/vendorcode/amd/pi/00670F00" if AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON
@ -40,7 +39,6 @@ config AGESA_BINARY_PI_VENDORCODE_PATH
config AGESA_BINARY_PI_FILE
string "AGESA PI binary file name"
default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01
default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01
default "3rdparty/amd_blobs/stoneyridge/pi/CZ/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON
default "3rdparty/amd_blobs/stoneyridge/pi/ST/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON

6
src/vendorcode/amd/pi/Makefile.inc
View File

@ -30,7 +30,7 @@
subdirs-y += 00670F00
ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01),y)
ifeq ($(CONFIG_CPU_AMD_PI_00730F01),y)
# AGESA V5 Files
AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH))
@ -52,10 +52,6 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
ifeq ($(CONFIG_CPU_AMD_PI_00630F01),y)
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
endif
AGESA_INC += -I$(src)/northbridge/amd/pi
AGESA_INC += -I$(src)/southbridge/amd/pi/hudson