mb/google/volteer: Convert static ASL files to new DPTF implementation
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak
Patrick Georgi
parent
c34079cea0
commit
07ac2ec021
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@ -4,6 +4,13 @@
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#define _DRIVERS_INTEL_DPTF_CHIP_H_
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#include <acpi/acpigen_dptf.h>
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#include <timer.h> /* for MSECS_PER_SEC */
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#define DPTF_PASSIVE(src, tgt, tmp, prd) \
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{.source = DPTF_##src, .target = DPTF_##tgt, .temp = (tmp), .period = (prd)}
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#define DPTF_CRITICAL(src, tmp, typ) \
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{.source = DPTF_##src, .temp = (tmp), .type = DPTF_CRITICAL_##typ}
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#define TEMP_PCT(t, p) {.temp = (t), .fan_pct = (p)}
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struct drivers_intel_dptf_config {
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struct {
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@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_SX9310
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select DRIVERS_INTEL_DPTF
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select DRIVERS_INTEL_PMC
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select DRIVERS_I2C_MAX98373
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select DRIVERS_INTEL_SOUNDWIRE
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@ -52,17 +52,6 @@ DefinitionBlock(
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include Tiger Lake soc specific DPTF changes */
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#include <soc/intel/tigerlake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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#if CONFIG(VARIANT_HAS_MIPI_CAMERA)
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@ -282,7 +282,88 @@ chip soc/intel/tigerlake
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#From EDS(575683)
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device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
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device pci 02.0 on end # Graphics
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device pci 04.0 on end # DPTF 0x9A03
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device pci 04.0 on
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# Default DPTF Policy for all Volteer boards if not overridden
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chip drivers/intel/dptf
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## Active Policy
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register "policies.active[0]" = "{.target=DPTF_CPU,
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.thresholds={TEMP_PCT(85, 90),
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TEMP_PCT(80, 69),
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TEMP_PCT(75, 56),
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TEMP_PCT(70, 46),
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TEMP_PCT(65, 36),}}"
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register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
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.thresholds={TEMP_PCT(50, 90),
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TEMP_PCT(47, 69),
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TEMP_PCT(45, 56),
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TEMP_PCT(42, 46),
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TEMP_PCT(39, 36),}}"
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register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1,
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.thresholds={TEMP_PCT(50, 90),
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TEMP_PCT(47, 69),
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TEMP_PCT(45, 56),
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TEMP_PCT(42, 46),
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TEMP_PCT(39, 36),}}"
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register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2,
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.thresholds={TEMP_PCT(50, 90),
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TEMP_PCT(47, 69),
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TEMP_PCT(45, 56),
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TEMP_PCT(42, 46),
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TEMP_PCT(39, 36),}}"
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## Passive Policy
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register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
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register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
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register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 6000)"
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register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)"
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## Critical Policy
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register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)"
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register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
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register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)"
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register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)"
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## Power Limits Control
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# 10-15W PL1 in 200mW increments, avg over 28-32s interval
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# PL2 is fixed at 64W, avg over 28-32s interval
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register "controls.power_limits.pl1" = "{
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.min_power = 3000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,}"
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register "controls.power_limits.pl2" = "{
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.min_power = 15000,
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.max_power = 60000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf[0]" = "{ 255, 1700 }"
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register "controls.charger_perf[1]" = "{ 24, 1500 }"
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register "controls.charger_perf[2]" = "{ 16, 1000 }"
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register "controls.charger_perf[3]" = "{ 8, 500 }"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
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register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }"
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register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }"
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register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }"
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register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }"
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register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }"
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register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }"
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register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }"
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register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }"
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register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }"
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# Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 on end
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end
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end # DPTF 0x9A03
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device pci 05.0 off end # IPU 0x9A19
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device pci 06.0 off end # PEG60 0x9A09
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device pci 07.0 on end # TBT_PCIe0 0x9A23
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@ -1,148 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#define DPTF_CPU_PASSIVE 95
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#define DPTF_CPU_CRITICAL 105
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#define DPTF_CPU_ACTIVE_AC0 85
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#define DPTF_CPU_ACTIVE_AC1 80
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#define DPTF_CPU_ACTIVE_AC2 75
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#define DPTF_CPU_ACTIVE_AC3 70
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#define DPTF_CPU_ACTIVE_AC4 65
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
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#define DPTF_TSR0_PASSIVE 65
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#define DPTF_TSR0_CRITICAL 75
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#define DPTF_TSR0_ACTIVE_AC0 50
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#define DPTF_TSR0_ACTIVE_AC1 47
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#define DPTF_TSR0_ACTIVE_AC2 45
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#define DPTF_TSR0_ACTIVE_AC3 42
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#define DPTF_TSR0_ACTIVE_AC4 39
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
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#define DPTF_TSR1_PASSIVE 65
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#define DPTF_TSR1_CRITICAL 75
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#define DPTF_TSR1_ACTIVE_AC0 50
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#define DPTF_TSR1_ACTIVE_AC1 47
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#define DPTF_TSR1_ACTIVE_AC2 45
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#define DPTF_TSR1_ACTIVE_AC3 42
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#define DPTF_TSR1_ACTIVE_AC4 39
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor 3"
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#define DPTF_TSR2_PASSIVE 65
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#define DPTF_TSR2_CRITICAL 75
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#define DPTF_TSR2_ACTIVE_AC0 50
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#define DPTF_TSR2_ACTIVE_AC1 47
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#define DPTF_TSR2_ACTIVE_AC2 45
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#define DPTF_TSR2_ACTIVE_AC3 42
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#define DPTF_TSR2_ACTIVE_AC4 39
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#define DPTF_TSR3_SENSOR_ID 3
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#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor 4"
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#define DPTF_TSR3_PASSIVE 65
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#define DPTF_TSR3_CRITICAL 75
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#define DPTF_TSR3_ACTIVE_AC0 50
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#define DPTF_TSR3_ACTIVE_AC1 47
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#define DPTF_TSR3_ACTIVE_AC2 45
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#define DPTF_TSR3_ACTIVE_AC3 42
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#define DPTF_TSR3_ACTIVE_AC4 39
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
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Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
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Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
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Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
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})
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/* DFPS: Fan Performance States */
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Name (DFPS, Package () {
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0, // Revision
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/*
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* TODO : Need to update this Table after characterization.
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* These are initial reference values.
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*/
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {50, 0xFFFFFFFF, 3838, 90, 900},
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Package () {40, 0xFFFFFFFF, 2904, 55, 550},
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Package () {30, 0xFFFFFFFF, 2337, 30, 300},
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Package () {20, 0xFFFFFFFF, 1608, 15, 150},
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Package () {10, 0xFFFFFFFF, 800, 10, 100},
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Package () {0, 0xFFFFFFFF, 0, 0, 50}
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})
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Name (DART, Package () {
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/* Fan effect on CPU */
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0, // Revision
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Package () {
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/*
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* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
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* AC7, AC8, AC9
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*/
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\_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 0, 0,
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0, 0, 0
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}
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})
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
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/* CPU Throttle Effect on TSR1 sensor */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
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/* Charger Throttle Effect on Charger (TSR0) */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
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/* CPU Throttle Effect on TSR2 sensor */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
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/* CPU Throttle Effect on TSR3 sensor */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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3000, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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15000, /* PowerLimitMinimum */
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60000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/acpi/dptf.asl>
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@ -1,7 +0,0 @@
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/*
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*
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <baseboard/acpi/dptf.asl>
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