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mainboard/asus: Move F2A85-M_LE variant to F2A85-M. 

Note that M and M_PRO had same DefaultPlatformMemoryConfiguration
defined, use one for both.

Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18606
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2017-03-06 17:54:27 +02:00
parent 03e6a455a3
commit 07bc9f76bc
33 changed files with 75 additions and 724 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/mainboard/asus/f2a85-m/BiosCallOuts.c
View File

@ -42,6 +42,7 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
* Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
* the vendor BIOS.
*/
#if !IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
{0x11, 0x99430140},
{0x12, 0x411111f0},
@ -59,6 +60,25 @@ const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
{0x1f, 0x411111f0},
{0xff, 0xffffffff}
};
#else
const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
{0x11, 0x99430140},
{0x12, 0x411111f0},
{0x14, 0x01014010},
{0x15, 0x411111f0},
{0x16, 0x411111f0},
{0x17, 0x411111f0},
{0x18, 0x01a19850},
{0x19, 0x02a19c60},
{0x1a, 0x0181305f},
{0x1b, 0x02214c20},
{0x1c, 0x411111f0},
{0x1d, 0x4004c601},
{0x1e, 0x01456130},
{0x1f, 0x411111f0},
{0xff, 0xffffffff}
};
#endif
static const CODEC_TBL_LIST CodecTableList[] =
{

24
src/mainboard/asus/f2a85-m/Kconfig
View File

@ -14,7 +14,7 @@
# GNU General Public License for more details.
#
if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO
select BOARD_ROMSIZE_KB_8192
select GFXUMA
@ -62,6 +62,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
string
default "F2A85-M" if BOARD_ASUS_F2A85_M
default "F2A85-M_LE" if BOARD_ASUS_F2A85_M_LE
default "F2A85-M_PRO" if BOARD_ASUS_F2A85_M_PRO
config HW_MEM_HOLE_SIZEK
@ -92,6 +93,8 @@ config ONBOARD_VGA_IS_PRIMARY
bool
default y
if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
config VGA_BIOS_ID
string
default "1002,9993"
@ -104,9 +107,24 @@ config POST_IO
bool
default n
endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
if BOARD_ASUS_F2A85_M_LE
config VGA_BIOS_ID
string
default "1002,9901"
config VGA_BIOS_FILE
string
default "pci1002,9901.rom"
endif
config DEVICETREE
string
default "devicetree_f2a85-m_pro.cb" if BOARD_ASUS_F2A85_M_PRO
default "devicetree_f2a85-m.cb" if BOARD_ASUS_F2A85_M
default "devicetree_f2a85-m_le.cb" if BOARD_ASUS_F2A85_M_LE
endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE

3
src/mainboard/asus/f2a85-m/Kconfig.name
View File

@ -3,3 +3,6 @@ config BOARD_ASUS_F2A85_M
config BOARD_ASUS_F2A85_M_PRO
bool "F2A85-M PRO"
config BOARD_ASUS_F2A85_M_LE
bool "F2A85-M LE"

6
src/mainboard/asus/f2a85-m/OemCustomize.c
View File

@ -205,7 +205,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
*----------------------------------------------------------------------------------------
*/
#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M)
#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) || IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@ -225,7 +225,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
*/
PSO_END
};
#elif IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
#elif IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@ -234,7 +234,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
/*
TODO: is this OK for DDR3 socket FM2?

0
src/mainboard/asus/f2a85-m_le/devicetree.cb → src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
View File

52
src/mainboard/asus/f2a85-m/romstage.c
View File

@ -35,26 +35,16 @@
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
#include <string.h>
#if CONFIG_BOARD_ASUS_F2A85_M
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#endif /* CONFIG_BOARD_ASUS_F2A85_M */
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
#if CONFIG_BOARD_ASUS_F2A85_M
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#endif /* CONFIG_BOARD_ASUS_F2A85_M */
static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
@ -69,6 +59,23 @@ static void sbxxx_enable_48mhzout(void)
SB_MMIO_MISC32(0x40) = reg32;
}
static void superio_init_m(void)
{
pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
ite_kill_watchdog(gpio);
ite_enable_serial(uart, CONFIG_TTYS0_BASE);
ite_enable_3vsbsw(gpio);
}
static void superio_init_m_pro(void)
{
pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);
nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
@ -78,12 +85,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
#endif
#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
hudson_lpc_port80();
#endif
if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
hudson_pci_port80();
else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
@ -106,13 +111,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable SIO clock */
sbxxx_enable_48mhzout();
#if CONFIG_BOARD_ASUS_F2A85_M
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_3vsbsw(GPIO_DEV);
#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
#endif
if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
superio_init_m_pro();
else
superio_init_m();
console_init();
/* turn on secondary smbus at b20 */

103
src/mainboard/asus/f2a85-m_le/BiosCallOuts.c
View File

@ -1,103 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "AGESA.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <cbfs.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
#include <stdlib.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/**
* ASUS F2A85-M board ALC887-VD Verb Table
*
* Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
* the vendor BIOS.
*/
const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
{0x11, 0x99430140},
{0x12, 0x411111f0},
{0x14, 0x01014010},
{0x15, 0x411111f0},
{0x16, 0x411111f0},
{0x17, 0x411111f0},
{0x18, 0x01a19850},
{0x19, 0x02a19c60},
{0x1a, 0x0181305f},
{0x1b, 0x02214c20},
{0x1c, 0x411111f0},
{0x1d, 0x4004c601},
{0x1e, 0x01456130},
{0x1f, 0x411111f0},
{0xff, 0xffffffff}
};
static const CODEC_TBL_LIST CodecTableList[] =
{
{0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]},
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
};
/**
* Fch Oem setting callback
*
* Configure platform specific Hudson device,
* such Azalia, SATA, GEC, IMC etc.
*/
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
/* Azalia Controller OEM Codec Table Pointer */
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
/* Azalia Controller Front Panel OEM Table Pointer */
FchParams_env->Imc.ImcEnable = FALSE;
FchParams_env->Hwm.HwMonitorEnable = FALSE;
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
/* XHCI configuration */
FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
}
printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
}

93
src/mainboard/asus/f2a85-m_le/Kconfig
View File

@ -1,93 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
if BOARD_ASUS_F2A85_M_LE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F
select BOARD_ROMSIZE_KB_8192
select GFXUMA
select HUDSON_DISABLE_IMC
choice
prompt "DDR3 memory voltage"
default BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150
config BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135
bool "1.35V"
help
Set DRR3 memory voltage to 1.35V
config BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150
bool "1.50V"
help
Set DRR3 memory voltage to 1.50V
config BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165
bool "1.65V"
help
Set DRR3 memory voltage to 1.65V
endchoice
config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL
hex
default 0x9e if BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135
default 0x0 if BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150
default 0x1e if BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165
config MAINBOARD_DIR
string
default asus/f2a85-m_le
config MAINBOARD_PART_NUMBER
string
default "F2A85-M_LE"
config HW_MEM_HOLE_SIZEK
hex
default 0x200000
config MAX_CPUS
int
default 4
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
config IRQ_SLOT_COUNT
int
default 11
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config VGA_BIOS_ID
string
default "1002,9901"
config VGA_BIOS_FILE
string
default "pci1002,9901.rom"
endif # BOARD_ASUS_F2A85_M_LE

2
src/mainboard/asus/f2a85-m_le/Kconfig.name
View File

@ -1,2 +0,0 @@
config BOARD_ASUS_F2A85_M_LE
bool "F2A85-M LE"

22
src/mainboard/asus/f2a85-m_le/Makefile.inc
View File

@ -1,22 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
ramstage-y += buildOpts.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c

28
src/mainboard/asus/f2a85-m_le/OemCustomize.c
View File

@ -1,28 +0,0 @@
#include "../f2a85-m/OemCustomize.c"
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
*/
#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
/*
TODO: is this OK for DDR3 socket FM2?
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
*/
PSO_END
};
#endif /* CONFIG_BOARD_ASUS_F2A85M_LE */

0
src/mainboard/asus/f2a85-m_le/OptionsIds.h
View File

1
src/mainboard/asus/f2a85-m_le/PlatformGnbPcieComplex.h
View File

@ -1 +0,0 @@
#include "../f2a85-m/PlatformGnbPcieComplex.h"

1
src/mainboard/asus/f2a85-m_le/acpi/AmdImc.asl
View File

@ -1 +0,0 @@
#include "../../f2a85-m/acpi/AmdImc.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/cpstate.asl
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@ -1 +0,0 @@
#include "../../f2a85-m/acpi/cpstate.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/gpe.asl
View File

@ -1 +0,0 @@
#include "../../f2a85-m/acpi/gpe.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/mainboard.asl
View File

@ -1 +0,0 @@
#include "../../f2a85-m/acpi/mainboard.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/routing.asl
View File

@ -1 +0,0 @@
#include "../../f2a85-m/acpi/routing.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/sata.asl
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@ -1 +0,0 @@
#include "../../f2a85-m/acpi/sata.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/si.asl
View File

@ -1 +0,0 @@
#include "../../f2a85-m/acpi/si.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/sleep.asl
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@ -1 +0,0 @@
#include "../../f2a85-m/acpi/sleep.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/superio.asl
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@ -1 +0,0 @@
#include "../../f2a85-m/acpi/superio.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/thermal.asl
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@ -1 +0,0 @@
#include "../../f2a85-m/acpi/thermal.asl"

1
src/mainboard/asus/f2a85-m_le/acpi/usb_oc.asl
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@ -1 +0,0 @@
include "../../f2a85-m/acpi/usb_oc.asl"

1
src/mainboard/asus/f2a85-m_le/acpi_tables.c
View File

@ -1 +0,0 @@
#include "../f2a85-m/acpi_tables.c"

7
src/mainboard/asus/f2a85-m_le/board_info.txt
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@ -1,7 +0,0 @@
Category: desktop
Board URL: http://www.asus.com/Motherboards/F2A85M_LE/
ROM package: DIP8
ROM protocol: [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64BV.htm SPI]
ROM socketed: y
Flashrom support: y
Release year: 2013

347
src/mainboard/asus/f2a85-m_le/buildOpts.c
View File

@ -1,347 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/**
* @file
*
* AMD User options selection for a Brazos platform solution system
*
* This file is placed in the user's platform directory and contains the
* build option selections desired for that platform.
*
* For Information about this file, see @ref platforminstall.
*
*/
#include <stdlib.h>
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
/* Include the files that instantiate the configuration definitions. */
#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
/* the next two headers depend on heapManager.h */
#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
/* These tables are optional and may be used to adjust memory timing settings */
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
#define INSTALL_FM1_SOCKET_SUPPORT FALSE
#define INSTALL_FP2_SOCKET_SUPPORT FALSE
#define INSTALL_FT1_SOCKET_SUPPORT FALSE
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
#define BLDOPT_REMOVE_SRAT FALSE //TRUE
#define BLDOPT_REMOVE_SLIT FALSE //TRUE
#define BLDOPT_REMOVE_WHEA FALSE //TRUE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_DMI TRUE
//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
//This element selects whether P-States should be forced to be independent,
// as reported by the ACPI _PSD object. For single-link processors,
// setting TRUE for OS to support this feature.
//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
/* Build configuration values here.
*/
#define BLDCFG_VRM_CURRENT_LIMIT 90000
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
#define BLDCFG_PLAT_NUM_IO_APICS 3
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_MEM_INIT_PSTATE 0
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
#define BLDCFG_MEMORY_POWER_DOWN TRUE
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
#define BLDCFG_ONLINE_SPARE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
#define BLDCFG_ENABLE_ECC_FEATURE FALSE
#define BLDCFG_ECC_REDIRECTION FALSE
#define BLDCFG_SCRUB_DRAM_RATE 0
#define BLDCFG_SCRUB_L2_RATE 0
#define BLDCFG_SCRUB_L3_RATE 0
#define BLDCFG_SCRUB_IC_RATE 0
#define BLDCFG_SCRUB_DC_RATE 0
#define BLDCFG_ECC_SYMBOL_SIZE 4
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
#define BLDCFG_ECC_SYNC_FLOOD FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
#define BLDOPT_REMOVE_ALIB FALSE
#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
#define BLDCFG_CFG_ABM_SUPPORT 0
//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
// Specify the default values for the VRM controlling the VDDNB plane.
// If not specified, the values used for the core VRM will be applied
//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
#define BLDCFG_IOMMU_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
/*
* Customized OEM build configurations for FCH component
*/
// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
// #define BLDCFG_AZALIA_SSID 0x780D1022
// #define BLDCFG_SMBUS_SSID 0x780B1022
// #define BLDCFG_IDE_SSID 0x780C1022
// #define BLDCFG_SATA_AHCI_SSID 0x78011022
// #define BLDCFG_SATA_IDE_SSID 0x78001022
// #define BLDCFG_SATA_RAID5_SSID 0x78031022
// #define BLDCFG_SATA_RAID_SSID 0x78021022
// #define BLDCFG_EHCI_SSID 0x78081022
// #define BLDCFG_OHCI_SSID 0x78071022
// #define BLDCFG_LPC_SSID 0x780E1022
// #define BLDCFG_SD_SSID 0x78061022
// #define BLDCFG_XHCI_SSID 0x78121022
// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
// This is the delivery package title, "BrazosPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE*/
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/*
* Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build.
* Comment out or mark TRUE those features you want to REMOVE from the build.
*/
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_SD_SSID 0x78061022
#define DFLT_XHCI_SSID 0x78121022
#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
//#define FCH_NO_XHCI_SUPPORT FALSE
GPIO_CONTROL f2a85_m_gpio[] = {
// {183, Function1, PullUpB},
{-1}
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
/* Moving this include up will break AGESA. */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>

74
src/mainboard/asus/f2a85-m_le/cmos.layout
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@ -1,74 +0,0 @@
#*****************************************************************************
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#*****************************************************************************
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 983 984

1
src/mainboard/asus/f2a85-m_le/dsdt.asl
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#include "../f2a85-m/dsdt.asl"

1
src/mainboard/asus/f2a85-m_le/irq_tables.c
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#include "../f2a85-m/irq_tables.c"

1
src/mainboard/asus/f2a85-m_le/mainboard.c
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#include "../f2a85-m/mainboard.c"

1
src/mainboard/asus/f2a85-m_le/mptable.c
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#include <mainboard/asus/f2a85-m/mptable.c>

1
src/mainboard/asus/f2a85-m_le/romstage.c
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#include "../f2a85-m/romstage.c"