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nb/intel/pineview: Correct COMP register write 

Reference code does an and-or operation with zero as or-value, reading
and writing to the same address. The accessed register is 32-bit, and
reference code programs bits 22, 21, 20, 16 to zero. However, coreboot
code reads the value from bits 7..0 instead. Correct this.

Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-03-26 19:07:49 +01:00
parent b77f01642c
commit 07ccc8d9cd
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/intel/pineview/raminit.c
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@ -1401,8 +1401,8 @@ static void sdram_rcomp(struct sysinfo *s)
MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5));
FOR_EACH_RCOMP_GROUP(i) { FOR_EACH_RCOMP_GROUP(i) {
/* FIXME: This should be an _AND_OR */ /* POR values are zero */
MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71; MCHBAR8_AND(C0RCOMPCTRLx(i) + 2, ~0x71);
} }
if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) {