GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments 

When looking into possible reasons for a proposed revert [1], I noticed
that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`,
but the actual definition only uses three.

    $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output
    […]
    --
    src/vendorcode/amd/agesa/f10/AGESA.h:#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
    src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex}
    --
    src/vendorcode/amd/agesa/f10/AGESA.h:   *      PCIE_DDI_DATA_INITIALIZER (ConnectorType
    src/vendorcode/amd/agesa/f10/AGESA.h-   *    },
    --
    src/vendorcode/amd/agesa/f10/AGESA.h:   *      PCIE_DDI_DATA_INITIALIZER (ConnectorType
    src/vendorcode/amd/agesa/f10/AGESA.h-   *    }
    --
    […]

So remove the fourth argument in the comments. Luckily the compiler,
at least gcc, warns about a wrong number of arguments, and therefore
no incorrect code resulted from the wrong documentation.

[1] http://review.coreboot.org/#/c/3077/

Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3080
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Paul Menzel 2013-04-13 15:58:03 +02:00 committed by Ronald G. Minnich
parent 8764b0e1c0
commit 07e0f1bf1a
7 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/vendorcode/amd/agesa/f10/AGESA.h
View File

@ -792,13 +792,13 @@ typedef struct {
* { * {
* 0, //Descriptor flags * 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* }, * },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* } * }
* }; * };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {

4
src/vendorcode/amd/agesa/f14/AGESA.h
View File

@ -905,13 +905,13 @@ typedef struct {
* { * {
* 0, //Descriptor flags * 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* }, * },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* } * }
* }; * };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {

12
src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h
View File

@ -121,7 +121,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
@ -129,7 +129,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
@ -137,7 +137,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
@ -145,7 +145,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
@ -153,7 +153,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
@ -161,7 +161,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* @endcode * @endcode

4
src/vendorcode/amd/agesa/f15/AGESA.h
View File

@ -1173,13 +1173,13 @@ typedef struct {
* { * {
* 0, //Descriptor flags * 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* }, * },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* } * }
* }; * };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {

12
src/vendorcode/amd/agesa/f15/Include/GnbPage.h
View File

@ -139,7 +139,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
@ -147,7 +147,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
@ -155,7 +155,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
@ -163,7 +163,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
@ -171,7 +171,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
@ -179,7 +179,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* @endcode * @endcode

4
src/vendorcode/amd/agesa/f15tn/AGESA.h
View File

@ -1299,13 +1299,13 @@ typedef struct {
* { * {
* 0, //Descriptor flags * 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* }, * },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* } * }
* }; * };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {

12
src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
View File

@ -166,7 +166,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
@ -174,7 +174,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
@ -182,7 +182,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
@ -190,7 +190,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
@ -198,7 +198,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
@ -206,7 +206,7 @@
* { * {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* } * }
* } * }
* @endcode * @endcode