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mb/google/myst: Enable fingerprint on UART

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Add fingerprint into device tree. Also set RST to low per HW
requirement.

BUG=b:285799911
TEST=check ectool --name=cros_fp version.
RO version:    bloonchipper_v2.0.5938-197506c1
RO cros fwid:  CROS_FWID_MISSING
RW version:    bloonchipper_v2.0.14348-e5fb0b9
RW cros fwid:  bloonchipper_14931.0.0

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75629
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2023-06-06 11:06:51 +08:00 committed by Felix Held
parent a4ced631ec
commit 07ebe4ae02
3 changed files with 20 additions and 1 deletions
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1
src/mainboard/google/myst/Kconfig
View file

@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_WIFI_GENERIC
select DRIVERS_UART_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_SKUID

2
src/mainboard/google/myst/variants/baseboard/gpio.c
View file

@ -68,7 +68,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* WWAN_AUX_RST_L */
PAD_GPO(GPIO_39, HIGH),
/* SOC_FP_RST_L */
PAD_GPO(GPIO_40, HIGH),
PAD_GPO(GPIO_40, LOW),
/* GPIO_41 - GPIO_66: Not available */
/* GPIO_67 (Unused) */
PAD_NC(GPIO_67),

18
src/mainboard/google/myst/variants/myst/overridetree.cb
View file

@ -93,4 +93,22 @@ chip soc/amd/phoenix
device i2c 2a on end
end
end # I2C3
device ref uart_1 on
chip drivers/uart/acpi
register "name" = ""CRFP""
register "desc" = ""Fingerprint Reader""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cros-ec-uart""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_18)"
register "wake" = "GEVENT_14"
register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_40)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)"
register "enable_delay_ms" = "3"
device generic 0 alias fpmcu on
probe FP UART
end
end
end
end # chip soc/amd/phoenix