remove SMBUS_MEM_DEVICE_[START|END] traces from code.

add 8mbit example config for amd solo.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/config/Options.lb

@@ -514,26 +514,6 @@ define IDE_OFFSET
 	comment "Sector at which to start searching for boot image"
 end
 
-###############################################
-# SMBUS options
-###############################################
-
-define SMBUS_MEM_DEVICE_START
-	default (0xa << 3)
-	export always
-	comment "Start address of SMBUS device"
-end
-define SMBUS_MEM_DEVICE_END
-	default {SMBUS_MEM_DEVICE_START +1}
-	export always
-	comment "End address of SMBUS device"
-end
-define SMBUS_MEM_DEVICE_INC
-	default 1
-	export always
-	comment "Increment value SMBUS"
-end
-
 ###############################################
 # Misc options
 ###############################################

src/sdram/generic_dump_spd.c

@@ -1,3 +1,70 @@
+/*
+ * This code is derived from the Opteron boards' debug.c.
+ * It should go away either there or here, depending what fits better.
+ */
+
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+	int i;
+	print_debug("\r\n");
+	for(i = 0; i < 4; i++) {
+		unsigned device;
+		device = ctrl->channel0[i];
+		if (device) {
+			int j;
+			print_debug("dimm: "); 
+			print_debug_hex8(i); 
+			print_debug(".0: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = spd_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+		device = ctrl->channel1[i];
+		if (device) {
+			int j;
+			print_debug("dimm: "); 
+			print_debug_hex8(i); 
+			print_debug(".1: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = spd_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+	}
+}
+
+#if 0
 void dump_spd_registers(void)
 {
 	unsigned device;
@@ -23,3 +90,4 @@ void dump_spd_registers(void)
 		printk_debug("\n");
 	}
 }
+#endif

targets/amd/solo/.cvsignore

@@ -1 +1 @@
-solo
+solo*

targets/amd/solo/Config-8MBit.lb

@@ -0,0 +1,102 @@
+# This config file will build an image without normal/fallback mechanism
+# but with a kernel image builtin instead
+#
+# This has not been tested due to a bug in the SST49LF080A 
+
+loadoptions
+
+target solo-8mbit
+
+uses ARCH
+uses CONFIG_COMPRESS
+uses CONFIG_IOAPIC
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_UDELAY_TSC
+uses CPU_FIXUP
+uses FALLBACK_SIZE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_HARD_RESET
+uses i586
+uses i686
+uses INTEL_PPRO_MTRR
+uses HEAP_SIZE
+uses IRQ_SLOT_COUNT
+uses k7
+uses k8
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses CONFIG_SMP
+uses CONFIG_MAX_CPUS
+uses MEMORY_HOLE
+uses PAYLOAD_SIZE
+uses _RAMBASE
+uses _ROMBASE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_OFFSET
+uses ROM_SECTION_SIZE
+uses ROM_SIZE
+uses STACK_SIZE
+uses USE_FALLBACK_IMAGE
+uses USE_OPTION_TABLE
+uses HAVE_OPTION_TABLE
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses  DEFAULT_CONSOLE_LOGLEVEL
+uses  CONFIG_CONSOLE_SERIAL8250
+uses MAINBOARD
+uses CONFIG_CHIP_CONFIGURE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses LINUXBIOS_EXTRA_VERSION
+uses CC
+
+option CC="gcc -m32"
+
+option CONFIG_CHIP_CONFIGURE=1
+
+option  MAXIMUM_CONSOLE_LOGLEVEL=8
+option  DEFAULT_CONSOLE_LOGLEVEL=8
+option  CONFIG_CONSOLE_SERIAL8250=1
+
+option CPU_FIXUP=1
+option CONFIG_UDELAY_TSC=0
+option i686=1
+option i586=1
+option INTEL_PPRO_MTRR=1
+option k7=1
+option k8=1
+
+option ROM_SIZE=0x100000
+
+
+option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_STREAM=1
+option HAVE_FALLBACK_BOOT=1
+
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+option FALLBACK_SIZE=ROM_SIZE
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+
+romimage "single" 
+	option USE_FALLBACK_IMAGE=1
+	option ROM_IMAGE_SIZE=0x10000
+	option LINUXBIOS_EXTRA_VERSION=".0-8MBit"
+	mainboard amd/solo
+	payload /usr/share/LinuxBIOS/kernelpayload.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "single"
+