amd/stoneyridge: Make cbmem_top SMM aware
Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to HAVE_SMI_HANDLER. Change the value returned by cbmem_top() to carve out a range to be used by TSEG. The SMM Mask register has a granularity of 128KB but align the value to 16MB to keep down the number of variable MTRRs required. Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -289,7 +289,7 @@ config STONEYRIDGE_UART
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config SMM_TSEG_SIZE
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hex
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default 0x800000 if HAVE_SMI_HANDLER
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default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
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default 0x0
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config ACPI_CPU_STRING
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@ -41,5 +41,7 @@ void *cbmem_top(void)
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if (!tom.lo)
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return 0;
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else
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return (void *)restore_top_of_low_cacheable();
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/* 16MB alignment to keep MTRR usage low */
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return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
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- CONFIG_SMM_TSEG_SIZE, 16*MiB);
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}
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