amd/stoneyridge: Make cbmem_top SMM aware

Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to
HAVE_SMI_HANDLER.

Change the value returned by cbmem_top() to carve out a range to be
used by TSEG.  The SMM Mask register has a granularity of 128KB but
align the value to 16MB to keep down the number of variable MTRRs
required.

Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/amd/stoneyridge/Kconfig

@@ -289,7 +289,7 @@ config STONEYRIDGE_UART
 
 config SMM_TSEG_SIZE
 	hex
-	default 0x800000 if HAVE_SMI_HANDLER
+	default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
 	default 0x0
 
 config ACPI_CPU_STRING

src/soc/amd/stoneyridge/ramtop.c

@@ -41,5 +41,7 @@ void *cbmem_top(void)
 	if (!tom.lo)
 		return 0;
 	else
-		return (void *)restore_top_of_low_cacheable();
+		/* 16MB alignment to keep MTRR usage low */
+		return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
+				- CONFIG_SMM_TSEG_SIZE, 16*MiB);
 }