skylake: ACPI: Fix and clean up PCIE _PRT entries
Fix the code for PCIE _PRT entries to use an actual root port number from the device instead of NVS that was never initialized from zero. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados with pci=nomsi to ensure interrupts work Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295902 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11529 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
1bfbe7e72a
commit
0811230306
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@ -63,19 +63,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console
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PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
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GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
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RPA1, 32, // 0x30 - 0x33 - Root port address 1
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RPA2, 32, // 0x34 - 0x37 - Root port address 2
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RPA3, 32, // 0x38 - 0x3b - Root port address 3
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RPA4, 32, // 0x3c - 0x3f - Root port address 4
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RPA5, 32, // 0x40 - 0x43 - Root port address 5
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RPA6, 32, // 0x44 - 0x47 - Root port address 6
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RPA7, 32, // 0x48 - 0x4b - Root port address 7
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RPA8, 32, // 0x4c - 0x4f - Root port address 8
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RPA9, 32, // 0x50 - 0x53 - Root port address 9
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RPAA, 32, // 0x54 - 0x57 - Root port address 10
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RPAB, 32, // 0x58 - 0x5b - Root port address 11
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RPAC, 32, // 0x5c - 0x5f - Root port address 12
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DPTE, 8, // 0x60 - Enable DPTF
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DPTE, 8, // 0x30 - Enable DPTF
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/* ChromeOS specific */
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Offset (0x100),
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@ -24,56 +24,56 @@
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Method (IRQM, 1, Serialized) {
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/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
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Name (IQAA, Package() {
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Package() { 0x0000ffff, 0, 0, 16 },
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Package() { 0x0000ffff, 1, 0, 17 },
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Package() { 0x0000ffff, 2, 0, 18 },
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Package() { 0x0000ffff, 3, 0, 19 } })
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Name (IQAP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })
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Name (IQAA, Package () {
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Package () { 0x0000ffff, 0, 0, 16 },
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Package () { 0x0000ffff, 1, 0, 17 },
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Package () { 0x0000ffff, 2, 0, 18 },
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Package () { 0x0000ffff, 3, 0, 19 } })
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Name (IQAP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })
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/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
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Name (IQBA, Package() {
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Package() { 0x0000ffff, 0, 0, 17 },
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Package() { 0x0000ffff, 1, 0, 18 },
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Package() { 0x0000ffff, 2, 0, 19 },
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Package() { 0x0000ffff, 3, 0, 16 } })
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Name (IQBP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })
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Name (IQBA, Package () {
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Package () { 0x0000ffff, 0, 0, 17 },
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Package () { 0x0000ffff, 1, 0, 18 },
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Package () { 0x0000ffff, 2, 0, 19 },
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Package () { 0x0000ffff, 3, 0, 16 } })
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Name (IQBP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })
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/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
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Name (IQCA, Package() {
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Package() { 0x0000ffff, 0, 0, 18 },
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Package() { 0x0000ffff, 1, 0, 19 },
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Package() { 0x0000ffff, 2, 0, 16 },
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Package() { 0x0000ffff, 3, 0, 17 } })
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Name (IQCP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })
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Name (IQCA, Package () {
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Package () { 0x0000ffff, 0, 0, 18 },
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Package () { 0x0000ffff, 1, 0, 19 },
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Package () { 0x0000ffff, 2, 0, 16 },
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Package () { 0x0000ffff, 3, 0, 17 } })
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Name (IQCP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })
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/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
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Name (IQDA, Package() {
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Package() { 0x0000ffff, 0, 0, 19 },
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Package() { 0x0000ffff, 1, 0, 16 },
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Package() { 0x0000ffff, 2, 0, 17 },
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Package() { 0x0000ffff, 3, 0, 18 } })
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Name (IQDP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })
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Name (IQDA, Package () {
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Package () { 0x0000ffff, 0, 0, 19 },
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Package () { 0x0000ffff, 1, 0, 16 },
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Package () { 0x0000ffff, 2, 0, 17 },
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Package () { 0x0000ffff, 3, 0, 18 } })
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Name (IQDP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })
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Switch (ToInteger (Arg0)) {
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/* PCIe Root Port 1 and 5 */
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Case (Package() { 1, 5 }) {
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Switch (ToInteger (Arg0))
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{
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Case (Package () { 1, 5, 9 }) {
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If (PICM) {
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Return (IQAA)
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} Else {
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@ -81,8 +81,7 @@ Method (IRQM, 1, Serialized) {
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}
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}
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/* PCIe Root Port 2 and 6 */
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Case (Package() { 2, 6 }) {
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Case (Package () { 2, 6, 10 }) {
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If (PICM) {
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Return (IQBA)
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} Else {
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@ -90,8 +89,7 @@ Method (IRQM, 1, Serialized) {
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}
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}
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/* PCIe Root Port 3 and 7 */
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Case (Package() { 3, 7 }) {
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Case (Package () { 3, 7, 11 }) {
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If (PICM) {
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Return (IQCA)
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} Else {
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@ -99,8 +97,7 @@ Method (IRQM, 1, Serialized) {
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}
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}
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/* PCIe Root Port 4 and 8 */
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Case (Package() { 4, 8 }) {
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Case (Package () { 4, 8, 12 }) {
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If (PICM) {
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Return (IQDA)
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} Else {
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@ -120,90 +117,154 @@ Method (IRQM, 1, Serialized) {
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Device (RP01)
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{
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Name (_ADR, 0x001c0000)
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Name (_ADR, 0x001C0000)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA1))
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Return (IRQM (RPPN))
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}
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}
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Device (RP02)
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{
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Name (_ADR, 0x001c0001)
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Name (_ADR, 0x001C0001)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA2))
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Return (IRQM (RPPN))
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}
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}
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Device (RP03)
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{
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Name (_ADR, 0x001c0002)
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Name (_ADR, 0x001C0002)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA3))
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Return (IRQM (RPPN))
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}
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}
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Device (RP04)
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{
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Name (_ADR, 0x001c0003)
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Name (_ADR, 0x001C0003)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA4))
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Return (IRQM (RPPN))
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}
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}
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Device (RP05)
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{
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Name (_ADR, 0x001c0004)
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Name (_ADR, 0x001C0004)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA5))
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Return (IRQM (RPPN))
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}
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}
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Device (RP06)
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{
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Name (_ADR, 0x001c0005)
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Name (_ADR, 0x001C0005)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA6))
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Return (IRQM (RPPN))
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}
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}
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Device (RP07)
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{
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Name (_ADR, 0x001c0006)
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Name (_ADR, 0x001C0006)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA7))
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Return (IRQM (RPPN))
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}
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}
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Device (RP08)
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{
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Name (_ADR, 0x001c0007)
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Name (_ADR, 0x001C0007)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA8))
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Return (IRQM (RPPN))
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}
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}
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Device (RP09)
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{
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Name (_ADR, 0x001D0000)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPA9))
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Return (IRQM (RPPN))
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}
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}
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@ -211,9 +272,16 @@ Device (RP10)
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{
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Name (_ADR, 0x001D0001)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPAA))
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Return (IRQM (RPPN))
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}
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}
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@ -221,19 +289,32 @@ Device (RP11)
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{
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Name (_ADR, 0x001D0002)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPAB))
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Return (IRQM (RPPN))
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}
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}
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Device (RP12)
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{
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Name (_ADR, 0x001D0003)
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Name (_ADR, 0x001D0003)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPAC))
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Return (IRQM (RPPN))
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}
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}
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@ -55,10 +55,9 @@ typedef struct {
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u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
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u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
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u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
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u32 rpa[12]; /* 0x30 - 0x5f - Root Port Address */
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u8 dpte; /* 0x60 - Enable DPTF */
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u8 dpte; /* 0x30 - Enable DPTF */
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u8 unused[159];
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u8 unused[207];
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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