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skylake: ACPI: Fix and clean up PCIE _PRT entries 

Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work

Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-08-27 15:49:12 -07:00 committed by Patrick Georgi
parent 1bfbe7e72a
commit 0811230306
3 changed files with 155 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/skylake/acpi/globalnvs.asl
View File

@ -63,19 +63,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
RPA1, 32, // 0x30 - 0x33 - Root port address 1 DPTE, 8, // 0x30 - Enable DPTF
RPA2, 32, // 0x34 - 0x37 - Root port address 2
RPA3, 32, // 0x38 - 0x3b - Root port address 3
RPA4, 32, // 0x3c - 0x3f - Root port address 4
RPA5, 32, // 0x40 - 0x43 - Root port address 5
RPA6, 32, // 0x44 - 0x47 - Root port address 6
RPA7, 32, // 0x48 - 0x4b - Root port address 7
RPA8, 32, // 0x4c - 0x4f - Root port address 8
RPA9, 32, // 0x50 - 0x53 - Root port address 9
RPAA, 32, // 0x54 - 0x57 - Root port address 10
RPAB, 32, // 0x58 - 0x5b - Root port address 11
RPAC, 32, // 0x5c - 0x5f - Root port address 12
DPTE, 8, // 0x60 - Enable DPTF
/* ChromeOS specific */ /* ChromeOS specific */
Offset (0x100), Offset (0x100),

143
src/soc/intel/skylake/acpi/pcie.asl
View File

@ -71,9 +71,9 @@ Method (IRQM, 1, Serialized) {
Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 }, Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },
Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } }) Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })
Switch (ToInteger (Arg0)) { Switch (ToInteger (Arg0))
/* PCIe Root Port 1 and 5 */ {
Case (Package() { 1, 5 }) { Case (Package () { 1, 5, 9 }) {
If (PICM) { If (PICM) {
Return (IQAA) Return (IQAA)
} Else { } Else {
@ -81,8 +81,7 @@ Method (IRQM, 1, Serialized) {
} }
} }
/* PCIe Root Port 2 and 6 */ Case (Package () { 2, 6, 10 }) {
Case (Package() { 2, 6 }) {
If (PICM) { If (PICM) {
Return (IQBA) Return (IQBA)
} Else { } Else {
@ -90,8 +89,7 @@ Method (IRQM, 1, Serialized) {
} }
} }
/* PCIe Root Port 3 and 7 */ Case (Package () { 3, 7, 11 }) {
Case (Package() { 3, 7 }) {
If (PICM) { If (PICM) {
Return (IQCA) Return (IQCA)
} Else { } Else {
@ -99,8 +97,7 @@ Method (IRQM, 1, Serialized) {
} }
} }
/* PCIe Root Port 4 and 8 */ Case (Package () { 4, 8, 12 }) {
Case (Package() { 4, 8 }) {
If (PICM) { If (PICM) {
Return (IQDA) Return (IQDA)
} Else { } Else {
@ -120,90 +117,154 @@ Method (IRQM, 1, Serialized) {
Device (RP01) Device (RP01)
{ {
Name (_ADR, 0x001c0000) Name (_ADR, 0x001C0000)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA1)) Return (IRQM (RPPN))
} }
} }
Device (RP02) Device (RP02)
{ {
Name (_ADR, 0x001c0001) Name (_ADR, 0x001C0001)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA2)) Return (IRQM (RPPN))
} }
} }
Device (RP03) Device (RP03)
{ {
Name (_ADR, 0x001c0002) Name (_ADR, 0x001C0002)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA3)) Return (IRQM (RPPN))
} }
} }
Device (RP04) Device (RP04)
{ {
Name (_ADR, 0x001c0003) Name (_ADR, 0x001C0003)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA4)) Return (IRQM (RPPN))
} }
} }
Device (RP05) Device (RP05)
{ {
Name (_ADR, 0x001c0004) Name (_ADR, 0x001C0004)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA5)) Return (IRQM (RPPN))
} }
} }
Device (RP06) Device (RP06)
{ {
Name (_ADR, 0x001c0005) Name (_ADR, 0x001C0005)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA6)) Return (IRQM (RPPN))
} }
} }
Device (RP07) Device (RP07)
{ {
Name (_ADR, 0x001c0006) Name (_ADR, 0x001C0006)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA7)) Return (IRQM (RPPN))
} }
} }
Device (RP08) Device (RP08)
{ {
Name (_ADR, 0x001c0007) Name (_ADR, 0x001C0007)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA8)) Return (IRQM (RPPN))
} }
} }
Device (RP09) Device (RP09)
{ {
Name (_ADR, 0x001D0000) Name (_ADR, 0x001D0000)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPA9)) Return (IRQM (RPPN))
} }
} }
@ -211,9 +272,16 @@ Device (RP10)
{ {
Name (_ADR, 0x001D0001) Name (_ADR, 0x001D0001)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPAA)) Return (IRQM (RPPN))
} }
} }
@ -221,9 +289,16 @@ Device (RP11)
{ {
Name (_ADR, 0x001D0002) Name (_ADR, 0x001D0002)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT) Method (_PRT)
{ {
Return (IRQM (RPAB)) Return (IRQM (RPPN))
} }
} }
@ -231,9 +306,15 @@ Device (RP12)
{ {
Name (_ADR, 0x001D0003) Name (_ADR, 0x001D0003)
Method (_PRT) OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{ {
Return (IRQM (RPAC)) , 24,
} RPPN, 8, /* Root Port Number */
} }
Method (_PRT)
{
Return (IRQM (RPPN))
}
}

5
src/soc/intel/skylake/include/soc/nvs.h
View File

@ -55,10 +55,9 @@ typedef struct {
u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */ u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
u32 rpa[12]; /* 0x30 - 0x5f - Root Port Address */ u8 dpte; /* 0x30 - Enable DPTF */
u8 dpte; /* 0x60 - Enable DPTF */
u8 unused[159]; u8 unused[207];
/* ChromeOS specific (0x100 - 0xfff) */ /* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos; chromeos_acpi_t chromeos;