This patch adds the Supermicro H8QME-2+ (fam10) Motherboard with the
following remaining issues: - ACPI not working - SMBus gets irq 0 instead of 5 - Loading VGA rom fails (using seabios to do it) (copied a newer Makefile.inc from h8dmr_fam10 vs. the patch on the list) Signed-off-by: Knut Kujat <knuku@gap.upv.es> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Knut Kujat
Patrick Georgi
parent
5a559d4386
commit
081c8978ac
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@ -5,6 +5,7 @@ choice
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source "src/mainboard/supermicro/h8dme/Kconfig"
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source "src/mainboard/supermicro/h8dmr/Kconfig"
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source "src/mainboard/supermicro/h8dmr_fam10/Kconfig"
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source "src/mainboard/supermicro/h8qme_fam10/Kconfig"
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source "src/mainboard/supermicro/x6dai_g/Kconfig"
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source "src/mainboard/supermicro/x6dhe_g/Kconfig"
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source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
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@ -0,0 +1,349 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 AMD
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## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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# for testing with -O != s. FIXME
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#default CONFIG_XIP_ROM_SIZE = 128 * 1024
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default CONFIG_XIP_ROM_SIZE = 128 * 1024
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include /config/failovercalculation.lb
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#needed by irq_tables and mptable and acpi_tables
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object get_bus_conf.o
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if CONFIG_GENERATE_MP_TABLE object mptable.o end
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if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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end
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else
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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if CONFIG_USE_FAILOVER_IMAGE
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else
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if CONFIG_AP_CODE_IN_CAR
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makerule ./apc_auto.o
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depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
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end
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end
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## ROMSTRAP table for MCP55
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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end
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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ldscript /arch/i386/lib/failover_failover.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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end
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##
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## Setup RAM
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##
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if CONFIG_USE_INIT
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initobject auto.o
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else
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mainboardinit ./auto.inc
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end
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##
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## Include the secondary Configuration files
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##
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config chip.h
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dir /southbridge/nvidia/mcp55
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dir /southbridge/amd/amd8132
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chip northbridge/amd/amdfam10/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_F_1207
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdfam10 #mc0
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.0 on
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# SB on link 2.0
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chip southbridge/nvidia/mcp55
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # SFI
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io 0x62 = 0x100
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end
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device pnp 2e.7 off # GPIO_GAME_MIDI
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # WDTO_PLED
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device pnp 2e.9 off end # GPIO_SUSLED
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1.1 on # SM 0
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# chip drivers/generic/generic #dimm 0-0-0
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #dimm 0-0-1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-0
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-1
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# device i2c 57 on end
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# end
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# chip drivers/generic/generic #dimm 2-0-0
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# device i2c 58 on end
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# end
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# chip drivers/generic/generic #dimm 2-0-1
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# device i2c 59 on end
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# end
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# chip drivers/generic/generic #dimm 2-1-0
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# device i2c 5a on end
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# end
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# chip drivers/generic/generic #dimm 2-1-1
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# device i2c 5b on end
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# end
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# chip drivers/generic/generic #dimm 3-0-0
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# device i2c 5c on end
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# end
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# chip drivers/generic/generic #dimm 3-0-1
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# device i2c 5d on end
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# end
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# chip drivers/generic/generic #dimm 3-1-0
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# device i2c 5e on end
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# end
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# chip drivers/generic/generic #dimm 3-1-1
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# device i2c 5f on end
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# end
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end # SM
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device pci 1.1 on # SM 1
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#PCI device smbus address will diepend on addon pci device, do we need to scan_smbus_bus?
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#
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chip drivers/generic/generic #MAC EEPROM
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device i2c 51 on end
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end
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end # SM
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 on end # IDE
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device pci 5.0 on end # SATA 0
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device pci 5.1 on end # SATA 1
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device pci 5.2 on end # SATA 2
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device pci 6.1 off end # AZA
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device pci 7.0 on
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device pci 1.0 on end
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end
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device pci 8.0 off end
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device pci 9.0 off end
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device pci a.0 on end # PCI E 5
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device pci b.0 on end # PCI E 4
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device pci c.0 on end # PCI E 3
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device pci d.0 on end # PCI E 2
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device pci e.0 on end # PCI E 1
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device pci f.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_addr" = "0x51"
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end
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 19.0 on end
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device pci 19.0 on end
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device pci 19.0 on
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chip southbridge/amd/amd8132
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on
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device pci 3.0 on end
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device pci 3.1 on end
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end
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device pci 1.1 on end
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end #amd8132
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end #device pci 19.0
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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device pci 19.4 on end
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end # mc0
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end # PCI domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 off end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 on end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# device pnp 0.8 off end # io
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# device pnp 0.9 on end # io
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# end
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end #root_complex
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@ -0,0 +1,143 @@
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config BOARD_SUPERMICRO_H8QME_FAM10
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bool "H8QME-2+ (Fam10)"
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select ARCH_X86
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select CPU_AMD_SOCKET_F_1207
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select NORTHBRIDGE_AMD_AMDFAM10
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select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
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select SOUTHBRIDGE_NVIDIA_MCP55
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select SUPERIO_WINBOND_W83627HF
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select USE_PRINTK_IN_CAR
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select USE_DCACHE_RAM
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select HAVE_HARD_RESET
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select LIFT_BSP_APIC_ID
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select AMDMCT
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select BOARD_ROMSIZE_KB_1024
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select TINY_BOOTBLOCK
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select ENABLE_APIC_EXT_ID
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config MAINBOARD_DIR
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string
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default supermicro/h8qme_fam10
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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config DCACHE_RAM_BASE
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hex
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default 0xc4000
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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config DCACHE_RAM_SIZE
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hex
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default 0x0c000
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x04000
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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||||
config RAMBASE
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hex
|
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default 0x200000
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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config RAMTOP
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hex
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default 0x1000000
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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config HEAP_SIZE
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hex
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default 0xc0000
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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config APIC_ID_OFFSET
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hex
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default 0x0
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
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||||
config MEM_TRAIN_SEQ
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int
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default 2
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depends on BOARD_SUPERMICRO_H8QME_FAM10
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||||
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||||
config SB_HT_CHAIN_ON_BUS0
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int
|
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default 2
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depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
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||||
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
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bool
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default n
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||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config LB_CKS_RANGE_END
|
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int
|
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default 122
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config LB_CKS_LOC
|
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int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
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config MAINBOARD_PART_NUMBER
|
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string
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default "H8QME-2+ (Fam10)"
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
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hex
|
||||
default 0x100000
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 16
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x20
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x1
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config AMD_UCODE_PATCH_FILE
|
||||
string
|
||||
default "mc_patch_0100009f.h"
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config SERIAL_CPU_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x1511
|
||||
depends on BOARD_SUPERMICRO_H8QME_FAM10
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
|
||||
## the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
## MA 02110-1301 USA
|
||||
##
|
||||
|
||||
driver-y += mainboard.o
|
||||
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
obj-y += get_bus_conf.o
|
||||
obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
|
||||
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
# FIXME in $(top)/Makefile
|
||||
crt0s := $(src)/cpu/x86/32bit/entry32.inc
|
||||
crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
|
||||
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc
|
||||
|
||||
ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscripts += $(src)/cpu/x86/32bit/entry32.lds
|
||||
ldscripts += $(src)/arch/i386/lib/failover.lds
|
||||
|
||||
ifdef POST_EVALUATION
|
||||
|
||||
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
mv dsdt.hex $@
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
|
||||
|
||||
$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
|
||||
iasl -p $(obj)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/pci2.hex
|
||||
mv $(obj)/pci2.hex $(obj)/ssdt2.c
|
||||
|
||||
$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
|
||||
iasl -p $(obj)/pci3 -tc $(CONFIG_MAINBOARD)/
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/pci3.hex
|
||||
mv $(obj)/pci3.hex $(obj)/ssdt3.c
|
||||
|
||||
$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
|
||||
iasl -p $(obj)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/pci4.hex
|
||||
mv $(obj)/pci4.hex $(obj)/ssdt4.c
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_ACPI_SSDTX_NUM
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_USE_FAILOVER_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_FAILOVER_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_FAILOVER_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_VGA
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_VGA_ROM_RUN
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SERIAL_CPU_INIT
|
||||
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
||||
uses CONFIG_RAMTOP
|
||||
|
||||
uses CONFIG_UNCOMPRESSED
|
||||
|
||||
uses CONFIG_PCI_BUS_SEGN_BITS
|
||||
|
||||
uses CONFIG_AP_CODE_IN_CAR
|
||||
|
||||
uses CONFIG_MEM_TRAIN_SEQ
|
||||
|
||||
uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
||||
|
||||
uses CONFIG_AMDMCT
|
||||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_AMD_UCODE_PATCH_FILE
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
default CONFIG_PIRQ_ROUTE = 1
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=1024*1024
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use
|
||||
default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_FAILOVER_SIZE=0x02000
|
||||
|
||||
#more 1M for pgtbl
|
||||
default CONFIG_RAMTOP=16384*1024
|
||||
#default CONFIG_RAMTOP=16384*8192
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
default CONFIG_HAVE_FAILOVER_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
##default CONFIG_GENERATE_MP_TABLE=1
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
## ACPI tables will be included
|
||||
default CONFIG_GENERATE_ACPI_TABLES=0
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=4
|
||||
default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
default CONFIG_SERIAL_CPU_INIT=1
|
||||
|
||||
default CONFIG_ENABLE_APIC_EXT_ID=1
|
||||
default CONFIG_APIC_ID_OFFSET=0x00
|
||||
default CONFIG_LIFT_BSP_APIC_ID=1
|
||||
|
||||
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
|
||||
#2G
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
|
||||
#1G
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
#512M
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
|
||||
|
||||
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
|
||||
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_VGA=0
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_VGA_ROM_RUN=1
|
||||
default CONFIG_PCI_ROM_RUN=0
|
||||
|
||||
#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=1
|
||||
|
||||
#real SB Unit ID, default is 0x20, mean dont touch it at last
|
||||
#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
|
||||
|
||||
#make the SB HT chain on bus 0, default is not (0)
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
|
||||
|
||||
#only offset for SB chain?, default is yes(1)
|
||||
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#allow capable device use that above 4G
|
||||
#default CONFIG_PCI_64BIT_PREF_MEM=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc4000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x0c000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
default CONFIG_MEM_TRAIN_SEQ=2
|
||||
default CONFIG_WAIT_BEFORE_CPUS_INIT=0
|
||||
default CONFIG_AMDMCT = 1
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="h8qme (Fam10)"
|
||||
default CONFIG_MAINBOARD_VENDOR="Supermicro"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
|
||||
|
||||
##
|
||||
## Set microcode patch file name
|
||||
##
|
||||
## Barcelona rev Ax: "mc_patch_01000020.h"
|
||||
## Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
|
||||
## Barcelona rev B2, B3: "mc_patch_01000083.h"
|
||||
## Shanghai rev RB-C2: "mc_patch_01000086.h"
|
||||
## Shanghai rev DA-C2: "mc_patch_0100009f.h"
|
||||
##
|
||||
#default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000086.h"
|
||||
default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h"
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 0x1e000
|
||||
|
||||
|
||||
default CONFIG_STACK_SIZE=0x10000
|
||||
default CONFIG_HEAP_SIZE= 0xc000
|
||||
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00200000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
#default CONFIG_COMPRESSED_PAYLOAD = 1
|
||||
|
||||
# CBFS will take care of payload compression
|
||||
default CONFIG_UNCOMPRESSED = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
#default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_USE_FAILOVER_IMAGE=0
|
||||
default CONFIG_USE_FALLBACK_IMAGE=0
|
||||
default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
#define __PRE_RAM__
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
|
||||
|
||||
#define SET_NB_CFG_54 1
|
||||
|
||||
//used by raminit
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "lib/uart8250.c"
|
||||
#include "console/vtxprintf.c"
|
||||
#include "./arch/i386/lib/printk_init.c"
|
||||
|
||||
#if 0
|
||||
static void post_code(uint8_t value) {
|
||||
#if 1
|
||||
int i;
|
||||
for(i=0;i<0x80000;i++) {
|
||||
outb(value, 0x80);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
||||
//#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "northbridge/amd/amkfam10/raminit.h"
|
||||
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
|
||||
#include "lib/delay.c"
|
||||
|
||||
//#include "cpu/x86/lapic/boot_cpu.c"
|
||||
|
||||
//#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdfam10/reset_test.c"
|
||||
|
||||
//#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "northbridge/amd/amdfam10/debug.c"
|
||||
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||
|
||||
//#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||
#include "northbridge/amd/amdfam10/amdfam10.h"
|
||||
|
||||
#include "cpu/x86/mtrr.h"
|
||||
#include "cpu/amd/mtrr.h"
|
||||
#include "cpu/x86/tsc.h"
|
||||
|
||||
//#include "northbridge/amd/amdk8/amdk8_f_pci.c"
|
||||
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit_f_dqs.c"
|
||||
//#include "northbridge/amd/amdfam10/raminit_f_dqs.c"
|
||||
|
||||
static inline unsigned get_nodes(void)
|
||||
{
|
||||
return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
|
||||
}
|
||||
|
||||
//#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
void hardwaremain(int ret_addr)
|
||||
{
|
||||
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
|
||||
struct sys_info *sysinfox = ((CONFIG_RAMTOP) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
|
||||
|
||||
struct node_core_id id;
|
||||
|
||||
id = get_node_core_id_x();
|
||||
|
||||
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
|
||||
|
||||
train_ram(id.nodeid, sysinfo, sysinfox);
|
||||
|
||||
/*
|
||||
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
|
||||
*/
|
||||
|
||||
__asm__ volatile (
|
||||
"movl %0, %%edi\n\t"
|
||||
"jmp *%%edi\n\t"
|
||||
:: "a"(ret_addr)
|
||||
);
|
||||
|
||||
|
||||
|
||||
}
|
||||
struct eregs {
|
||||
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
|
||||
uint32_t vector;
|
||||
uint32_t error_code;
|
||||
uint32_t eip;
|
||||
uint32_t cs;
|
||||
uint32_t eflags;
|
||||
};
|
||||
|
||||
void x86_exception(struct eregs *info)
|
||||
{
|
||||
do {
|
||||
hlt();
|
||||
} while(1);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,380 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
#define __PRE_RAM__
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
|
||||
#define FAM10_SCAN_PCI_BUS 0
|
||||
#define FAM10_ALLOCATE_IO_RANGE 1
|
||||
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#define SET_NB_CFG_54 1
|
||||
#endif
|
||||
|
||||
#define FAM10_SET_FIDVID 1
|
||||
#define FAM10_SET_FIDVID_CORE_RANGE 0
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
// for enable the FAN
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
|
||||
|
||||
static void post_code(u8 value) {
|
||||
outb(value, 0x80);
|
||||
}
|
||||
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==0
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "lib/ramtest.c"
|
||||
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
|
||||
//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
|
||||
#include "northbridge/amd/amdfam10/raminit.h"
|
||||
#include "northbridge/amd/amdfam10/amdfam10.h"
|
||||
|
||||
#endif
|
||||
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdfam10/reset_test.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
|
||||
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==0
|
||||
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#include "northbridge/amd/amdfam10/debug.c"
|
||||
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
|
||||
|
||||
#include "northbridge/amd/amdfam10/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdfam10/amdfam10.h"
|
||||
#include "northbridge/amd/amdht/ht_wrapper.c"
|
||||
|
||||
#include "include/cpu/x86/mem.h"
|
||||
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
|
||||
#include "northbridge/amd/amdfam10/raminit_amdmct.c"
|
||||
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
|
||||
|
||||
#include "resourcemap.c"
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
#define MCP55_NUM 1
|
||||
#define MCP55_USE_NIC 1
|
||||
#define MCP55_USE_AZA 1
|
||||
|
||||
#define MCP55_PCI_E_X_0 4
|
||||
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
||||
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
|
||||
#include "cpu/amd/model_10xxx/init_cpus.c"
|
||||
|
||||
#include "cpu/amd/model_10xxx/fidvid.c"
|
||||
|
||||
#endif
|
||||
|
||||
#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
|
||||
|
||||
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
|
||||
#include "northbridge/amd/amdfam10/early_ht.c"
|
||||
|
||||
|
||||
static void sio_setup(void)
|
||||
{
|
||||
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
enable_smbus();
|
||||
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
|
||||
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
|
||||
dword |= (1<<0);
|
||||
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
|
||||
dword |= (1<<16);
|
||||
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
|
||||
|
||||
}
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
|
||||
sio_setup();
|
||||
|
||||
/* Setup the mcp55 */
|
||||
mcp55_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
#if CONFIG_HAVE_FAILOVER_BOOT==1
|
||||
__asm__ volatile ("jmp __fallback_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
)
|
||||
#endif
|
||||
;
|
||||
}
|
||||
#endif
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
#if CONFIG_HAVE_FAILOVER_BOOT==1
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if CONFIG_USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==0
|
||||
#include "spd_addr.h"
|
||||
#include "cpu/amd/microcode/microcode.c"
|
||||
#include "cpu/amd/model_10xxx/update_microcode.c"
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
|
||||
u32 bsp_apicid = 0;
|
||||
u32 val;
|
||||
u32 wants_reset;
|
||||
msr_t msr;
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
pnp_enter_ext_func_mode(SERIAL_DEV);
|
||||
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
|
||||
w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
pnp_exit_ext_func_mode(SERIAL_DEV);
|
||||
|
||||
uart_init();
|
||||
console_init();
|
||||
printk_debug("\n");
|
||||
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
val = cpuid_eax(1);
|
||||
printk_debug("BSP Family_Model: %08x \n", val);
|
||||
printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
|
||||
printk_debug("bsp_apicid = %02x \n", bsp_apicid);
|
||||
printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
update_microcode(val);
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR();
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
* It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
* I think it could be done by putting the spinlock flag in the cache
|
||||
* of the BSP located right after sysinfo.
|
||||
*/
|
||||
|
||||
wait_all_core0_started();
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk_debug("start_other_cores()\n");
|
||||
start_other_cores();
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
#if FAM10_SET_FIDVID == 1
|
||||
msr = rdmsr(0xc0010071);
|
||||
printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only
|
||||
* need to be done once.*/
|
||||
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr=rdmsr(0xc0010071);
|
||||
printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
wants_reset = mcp55_early_setup_x();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
print_info("...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset_x - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
if (wants_reset)
|
||||
printk_debug("mcp55_early_setup_x wanted additional reset!\n");
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk_debug("fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x3D);
|
||||
|
||||
//printk_debug("enable_smbus()\n");
|
||||
// enable_smbus(); /* enable in sio_setup */
|
||||
|
||||
post_code(0x3E);
|
||||
|
||||
memreset_setup();
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
|
||||
printk_debug("raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
post_code(0x41);
|
||||
|
||||
// printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x42); // Should never see this post code.
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations mainboard_ops;
|
||||
|
||||
struct mainboard_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 quad_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 reserved_memory1
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 200Mhz
|
||||
8 1 166Mhz
|
||||
8 2 133Mhz
|
||||
8 3 100Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
chip northbridge/amd/amdfam10/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_F_1207
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdfam10 #mc0
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on
|
||||
# SB on link 2.0
|
||||
chip southbridge/nvidia/mcp55
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # SFI
|
||||
io 0x62 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GPIO_GAME_MIDI
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # WDTO_PLED
|
||||
device pnp 2e.9 off end # GPIO_SUSLED
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 1.1 on # SM 1
|
||||
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
|
||||
# chip drivers/generic/generic #PCIXA Slot1
|
||||
# device i2c 50 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot1
|
||||
# device i2c 51 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot2
|
||||
# device i2c 52 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCI Slot1
|
||||
# device i2c 53 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Master MCP55 PCI-E
|
||||
# device i2c 54 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Slave MCP55 PCI-E
|
||||
# device i2c 55 on end
|
||||
# end
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on # PCI
|
||||
device pci 6.0 on end
|
||||
end
|
||||
device pci 6.1 on end # AZA
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 on end # NIC
|
||||
device pci a.0 on # PCI E 5
|
||||
device pci 0.0 on #nec pci-x
|
||||
end
|
||||
device pci 0.1 on #nec pci-x
|
||||
device pci 4.0 on end #scsi
|
||||
device pci 4.1 on end #scsi
|
||||
end
|
||||
end
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
|
||||
register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end # device pci 18.0
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
device pci 19.4 on end
|
||||
end # mc0
|
||||
|
||||
end # PCI domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 off end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 on end # io
|
||||
# end
|
||||
end #root_complex
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/quadcore.h>
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
struct mb_sysconf_t mb_sysconf;
|
||||
|
||||
/* Here you only need to set value in pci1234 for HT-IO that could be
|
||||
installed or not You may need to preset pci1234 for HTIO board, please
|
||||
refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */
|
||||
static u32 pci1234x[] = {
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc,
|
||||
};
|
||||
|
||||
|
||||
/* HT Chain device num, actually it is unit id base of every ht device
|
||||
in chain, assume every chain only have 4 ht device at most */
|
||||
|
||||
static unsigned hcdnx[] = {
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020,
|
||||
};
|
||||
|
||||
unsigned sbdn3;
|
||||
|
||||
|
||||
extern void get_pci1234(void);
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
device_t dev;
|
||||
int i, j;
|
||||
|
||||
if(get_bus_conf_done==1) return; //do it only once
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.mb = &mb_sysconf;
|
||||
|
||||
m = sysconf.mb;
|
||||
memset(m, 0, sizeof(struct mb_sysconf_t));
|
||||
|
||||
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
|
||||
for(i=0;i<sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_pci1234();
|
||||
|
||||
m->bus_type[0] = 1; //pci
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
|
||||
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
|
||||
|
||||
|
||||
m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
|
||||
sbdn3 =(sysconf.hcdn[1] & 0xff); // first byte of second chain
|
||||
|
||||
/* MCP55 */
|
||||
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
|
||||
|
||||
if (dev) {
|
||||
m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
|
||||
}
|
||||
|
||||
for(i=2; i<8;i++) {
|
||||
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
|
||||
if (dev) {
|
||||
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
|
||||
}
|
||||
}
|
||||
|
||||
/*8132_1*/
|
||||
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,0));
|
||||
m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
m->bus_8132_2++;
|
||||
/*8132_2*/
|
||||
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,0));
|
||||
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
m->bus_isa++;
|
||||
|
||||
for(i=0; i< sysconf.hc_possible_num; i++) {
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
|
||||
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
|
||||
for (j = busn; j <= busn_max; j++)
|
||||
m->bus_type[j] = 1;
|
||||
if(m->bus_isa <= busn_max)
|
||||
m->bus_isa = busn_max + 1;
|
||||
printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
|
||||
}
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
m->apicid_mcp55 = apicid_base+0;
|
||||
m->apicid_8132_1 = apicid_base+1;
|
||||
m->apicid_8132_2 = apicid_base+2;
|
||||
}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* This file was generated by getpir.c, do not modify!
|
||||
* (but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
unsigned slot_num;
|
||||
uint8_t *v;
|
||||
struct mb_sysconf_t *m;
|
||||
unsigned sbdn;
|
||||
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
sbdn = sysconf.sbdn;
|
||||
m = sysconf.mb;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = m->bus_mcp55[0];
|
||||
pirq->rtr_devfn = ((sbdn+6)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x10de;
|
||||
pirq->rtr_device = 0x0364;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
//pci bridge
|
||||
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
for(i=1; i< sysconf.hc_possible_num; i++) {
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
unsigned devn = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
}
|
||||
|
||||
#if CONFIG_CBB
|
||||
write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
if(sysconf.nodes>32) {
|
||||
write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
}
|
||||
#endif
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
return (unsigned long) pirq_info;
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("Supermicro H8QME Mainboard (Family 10)")
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MB_SYSCONF_H
|
||||
#define MB_SYSCONF_H
|
||||
|
||||
struct mb_sysconf_t {
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_mcp55[8]; //1
|
||||
unsigned apicid_mcp55;
|
||||
unsigned bus_type[256];
|
||||
|
||||
unsigned char bus_8132_0; //7
|
||||
unsigned char bus_8132_1; //8
|
||||
unsigned char bus_8132_2; //9
|
||||
unsigned apicid_8132_1;
|
||||
unsigned apicid_8132_2;
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
extern unsigned sbdn3;
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "SUPERMIC";
|
||||
static const char productid[12] = "H8QME ";
|
||||
struct mp_config_table *mc;
|
||||
struct mb_sysconf_t *m;
|
||||
unsigned sbdn;
|
||||
|
||||
|
||||
int i,j;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
sbdn = sysconf.sbdn;
|
||||
m = sysconf.mb;
|
||||
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
for(j= 0; j < 256 ; j++) {
|
||||
if(m->bus_type[j])
|
||||
smp_write_bus(mc, j, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, m->bus_isa, "ISA ");
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
//void smp_write_ioapic(struct mp_config_table *mc, unsigned char id, unsigned char ver, unsigned long apicaddr);
|
||||
|
||||
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
|
||||
|
||||
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
|
||||
}
|
||||
|
||||
dword = 0x00000ab5;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = 0x5ab0a500;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0xa000000b;
|
||||
dword = 0x10000002;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
|
||||
}
|
||||
|
||||
/* 8132_1*/
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,1));
|
||||
res = find_resource(dev,PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
|
||||
|
||||
/* 8132_2*/
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,1));
|
||||
res = find_resource(dev,PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID * PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus! Not correctly assign!!*/
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
|
||||
|
||||
|
||||
for(j=7;j>=2; j--) {
|
||||
if(!m->bus_mcp55[j]) continue;
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
|
||||
}
|
||||
}
|
||||
|
||||
for(j=0; j<1; j++)
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
static void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// WARD CHANGED
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// WARD CHANGED
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
// WARD CHANGED
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file defines the SPD addresses for the mainboard. Must be included in
|
||||
* cache_as_ram_auto.c
|
||||
*/
|
||||
|
||||
#define RC00 0
|
||||
#define RC01 1
|
||||
#define RC02 2
|
||||
#define RC03 3
|
||||
#define RC04 4
|
||||
#define RC05 5
|
||||
#define RC06 6
|
||||
#define RC07 7
|
||||
#define RC08 8
|
||||
#define RC09 9
|
||||
#define RC10 10
|
||||
#define RC11 11
|
||||
#define RC12 12
|
||||
#define RC13 13
|
||||
#define RC14 14
|
||||
#define RC15 15
|
||||
#define RC16 16
|
||||
#define RC17 17
|
||||
#define RC18 18
|
||||
#define RC19 19
|
||||
#define RC20 20
|
||||
#define RC21 21
|
||||
#define RC22 22
|
||||
#define RC23 23
|
||||
#define RC24 24
|
||||
#define RC25 25
|
||||
#define RC26 26
|
||||
#define RC27 27
|
||||
#define RC28 28
|
||||
#define RC29 29
|
||||
#define RC30 30
|
||||
#define RC31 31
|
||||
|
||||
#define RC32 32
|
||||
#define RC33 33
|
||||
#define RC34 34
|
||||
#define RC35 35
|
||||
#define RC36 36
|
||||
#define RC37 37
|
||||
#define RC38 38
|
||||
#define RC39 39
|
||||
#define RC40 40
|
||||
#define RC41 41
|
||||
#define RC42 42
|
||||
#define RC43 43
|
||||
#define RC44 44
|
||||
#define RC45 45
|
||||
#define RC46 46
|
||||
#define RC47 47
|
||||
#define RC48 48
|
||||
#define RC49 49
|
||||
#define RC50 50
|
||||
#define RC51 51
|
||||
#define RC52 52
|
||||
#define RC53 53
|
||||
#define RC54 54
|
||||
#define RC55 55
|
||||
#define RC56 56
|
||||
#define RC57 57
|
||||
#define RC58 58
|
||||
#define RC59 59
|
||||
#define RC60 60
|
||||
#define RC61 61
|
||||
#define RC62 62
|
||||
#define RC63 63
|
||||
|
||||
|
||||
#define DIMM0 0x50
|
||||
#define DIMM1 0x51
|
||||
#define DIMM2 0x52
|
||||
#define DIMM3 0x53
|
||||
#define DIMM4 0x54
|
||||
#define DIMM5 0x55
|
||||
#define DIMM6 0x56
|
||||
#define DIMM7 0x57
|
||||
|
||||
|
||||
static const u8 spd_addr[] = {
|
||||
//first node
|
||||
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
//second node
|
||||
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 2
|
||||
// third node
|
||||
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
// forth node
|
||||
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
target h8qme_fam10
|
||||
mainboard supermicro/h8qme_fam10
|
||||
|
||||
romimage "normal"
|
||||
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
|
||||
payload ../seabios.elf
|
||||
# payload /home/knut/Documents/final/filo.elf
|
||||
# payload ../payload.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option CONFIG_USE_FALLBACK_IMAGE=1
|
||||
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
|
||||
payload ../seabios.elf
|
||||
# payload /home/knut/Documents/final/filo.elf
|
||||
# payload ../payload.elf
|
||||
end
|
||||
|
||||
romimage "failover"
|
||||
option CONFIG_USE_FAILOVER_IMAGE=1
|
||||
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
|
||||
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
|
||||
|
|
@ -0,0 +1 @@
|
|||
_h8qme_fam10
|
||||
Loading…
Reference in New Issue