soc/intel/cannonlake: Add serialio device config
Add SerialIO device mode configuration, device mode definition mirrored from FSP. Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -86,6 +86,43 @@ static const char *soc_acpi_name(struct device *dev)
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}
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#endif
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static void parse_devicetree(FSP_S_CONFIG *params)
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{
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struct device *dev = SA_DEV_ROOT;
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if (!dev) {
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printk(BIOS_ERR, "Could not find root device\n");
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return;
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}
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const config_t *config = dev->chip_info;
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const int SerialIoDev[] = {
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PCH_DEVFN_I2C0,
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PCH_DEVFN_I2C1,
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PCH_DEVFN_I2C2,
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PCH_DEVFN_I2C3,
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PCH_DEVFN_I2C4,
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PCH_DEVFN_I2C5,
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PCH_DEVFN_GSPI0,
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PCH_DEVFN_GSPI1,
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PCH_DEVFN_GSPI2,
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PCH_DEVFN_UART0,
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PCH_DEVFN_UART1,
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PCH_DEVFN_UART2
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};
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for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {
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dev = dev_find_slot(0, SerialIoDev[i]);
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if (!dev->enabled) {
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params->SerialIoDevMode[i] = PchSerialIoDisabled;
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continue;
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}
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params->SerialIoDevMode[i] = PchSerialIoPci;
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if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||
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config->SerialIoDevMode[i] == PchSerialIoHidden)
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params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
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}
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}
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void soc_init_pre_device(void *chip_info)
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{
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/* Perform silicon specific init. */
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@ -137,6 +174,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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const struct device *dev = SA_DEV_ROOT;
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const config_t *config = dev->chip_info;
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/* Parse device tree and enable/disable devices */
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parse_devicetree(params);
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/* Set USB OC pin to 0 first */
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for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
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params->Usb2OverCurrentPin[i] = 0;
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@ -20,6 +20,7 @@
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#include <intelblocks/gspi.h>
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#include <stdint.h>
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <soc/vr_config.h>
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@ -200,6 +201,30 @@ struct soc_intel_cannonlake_config {
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*/
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uint32_t PrmrrSize;
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uint8_t PmTimerDisabled;
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/*
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* SerialIO device mode selection:
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*
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* Device index:
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* PchSerialIoIndexI2C0
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* PchSerialIoIndexI2C1
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* PchSerialIoIndexI2C2
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* PchSerialIoIndexI2C3
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* PchSerialIoIndexI2C4
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* PchSerialIoIndexI2C5
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* PchSerialIoIndexSPI0
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* PchSerialIoIndexSPI1
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* PchSerialIoIndexSPI2
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* PchSerialIoIndexUART0
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* PchSerialIoIndexUART1
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* PchSerialIoIndexUART2
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*
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* Mode select:
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* PchSerialIoDisabled
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* PchSerialIoPci
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* PchSerialIoAcpi
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* PchSerialIoHidden
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*/
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uint8_t SerialIoDevMode[PchSerialIoIndexMAX];
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};
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typedef struct soc_intel_cannonlake_config config_t;
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SERIALIO_H_
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#define _SERIALIO_H_
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typedef enum {
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PchSerialIoDisabled,
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PchSerialIoPci,
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PchSerialIoAcpi,
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PchSerialIoHidden,
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} PCH_SERIAL_IO_MODE;
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typedef enum {
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PchSerialIoIndexI2C0,
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PchSerialIoIndexI2C1,
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PchSerialIoIndexI2C2,
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PchSerialIoIndexI2C3,
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PchSerialIoIndexI2C4,
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PchSerialIoIndexI2C5,
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PchSerialIoIndexSPI0,
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PchSerialIoIndexSPI1,
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PchSerialIoIndexSPI2,
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PchSerialIoIndexUART0,
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PchSerialIoIndexUART1,
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PchSerialIoIndexUART2,
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PchSerialIoIndexMAX
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} PCH_SERIAL_IO_CONTROLLER;
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#endif
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