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mb/facebook/monolith: Add support to read cpu temperature 

Read the CPU temperature from the EC.

For this board the EC support is limited to reading the CPU temperature
sensor at this moment. Events are not supported.

BUG=N/A
TEST=tested on facebook monolith using acpidbg

The TSR0._TMP method is returning the correct values.

Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Wim Vervoorn 2020-01-15 09:13:46 +01:00 committed by Patrick Georgi
parent 815611ef56
commit 0826e35a35
2 changed files with 89 additions and 1 deletions
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6
src/mainboard/facebook/monolith/acpi/dptf.asl
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@ -22,10 +22,14 @@
#define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC3 60
#define DPTF_CPU_ACTIVE_AC4 50 #define DPTF_CPU_ACTIVE_AC4 50
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "ITE8528_CPU"
#define DPTF_TSR0_PASSIVE DPTF_CPU_PASSIVE
#define DPTF_TSR0_CRITICAL DPTF_CPU_CRITICAL
Name (DTRT, Package () { Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()

84
src/mainboard/facebook/monolith/acpi/ec.asl
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@ -0,0 +1,84 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Eltan B.V.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* We only use the ERAM region to retrieve the CPU temperature. Otherwise the EC is not enabled
* The _GPE is pointing to the correct pin but the EC events are not enabled in coreboot or the
* EC.
*/
Device (EC0)
{
Name (_HID, EisaId ("PNP0C09"))
Name (_UID, 0)
Name (_GPE, GPE0_DW0_22)
Name (_CRS, ResourceTemplate () {
IO (Decode16, 0x62, 0x62, 0, 1)
IO (Decode16, 0x66, 0x66, 0, 1)
})
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Method (_REG, 2, NotSerialized)
{
}
OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF)
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x00),
CPUT, 8,
}
Method (TSRD, 1, Serialized)
{
/* Prevent iasl remarks about unused parameters */
Store(Arg0, Local0)
Store(Local0, Arg0)
Return (\_SB.DPTF.CTOK (CPUT))
}
/* Set Aux Trip Point 0 */
Method (PAT0, 2, Serialized)
{
/* Prevent iasl remarks about unused parameters */
Store(Arg0, Local0)
Store(Local0, Arg0)
Store(Arg1, Local0)
Store(Local0, Arg1)
}
/* Set Aux Trip Point 1 */
Method (PAT1, 2, Serialized)
{
/* Prevent iasl remarks about unused parameters */
Store(Arg0, Local0)
Store(Local0, Arg0)
Store(Arg1, Local0)
Store(Local0, Arg1)
}
/* Disable Aux Trip Point */
Method (PATD, 1, Serialized)
{
/* Prevent iasl remarks about unused parameters */
Store(Arg0, Local0)
Store(Local0, Arg0)
}
}