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southbridge/amd: add IS_ENABLED() around Kconfig symbol references 

Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth 2017-06-24 21:30:14 -06:00
parent 5f9c6734fc
commit 083504b66b
31 changed files with 61 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/southbridge/amd/agesa/hudson/acpi/fch.asl
View File

@ -62,7 +62,7 @@ Device(SDCN) {
Name(_ADR, 0x00140007)
} /* end SDCN */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/* 0:14.4 - PCI slot 1, 2, 3 */
Device(PIBR) {
@ -175,7 +175,7 @@ Method(_INI, 0) {
/* Determine the OS we're running on */
OSFL()
#if defined(CONFIG_HUDSON_IMC_FWM) && CONFIG_HUDSON_IMC_FWM
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#include "acpi/AmdImc.asl" /* Hudson IMC function */
ITZE() /* enable IMC Fan Control*/
#endif

4
src/southbridge/amd/agesa/hudson/acpi/usb.asl
View File

@ -50,7 +50,7 @@ Device(UOH6) {
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/* 0:14.5 - OHCI */
Device(UEH1) {
Name(_ADR, 0x00140005)
@ -64,7 +64,7 @@ Device(XHC0) {
Name(_PRW, Package() {0x0B, 4})
} /* end XHC0 */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/* 0:10.1 - XHCI 1*/
Device(XHC1) {
Name(_ADR, 0x00100001)

2
src/southbridge/amd/agesa/hudson/fadt.c
View File

@ -25,7 +25,7 @@
#include "hudson.h"
#include "smi.h"
#if CONFIG_HUDSON_LEGACY_FREE
#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
#else
#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)

2
src/southbridge/amd/agesa/hudson/hudson.c
View File

@ -181,7 +181,7 @@ static void hudson_init(void *chip_info)
static void hudson_final(void *chip_info)
{
#if !CONFIG_ACPI_ENABLE_THERMAL_ZONE
#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
/* AMD AGESA does not enable thermal zone, so we enable it here. */
enable_imc_thermal_zone();

4
src/southbridge/amd/agesa/hudson/imc.c
View File

@ -35,7 +35,7 @@ void imc_reg_init(void)
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
@ -43,7 +43,7 @@ void imc_reg_init(void)
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
#endif
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
UINT8 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;

2
src/southbridge/amd/agesa/hudson/spi.c
View File

@ -110,7 +110,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
spi_write(0x1E, 5);
spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
spi_write(0x1E, 6);

4
src/southbridge/amd/amd8111/acpi.c
View File

@ -89,7 +89,7 @@ static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buf
}
#if CONFIG_HAVE_ACPI_TABLES
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
unsigned pm_base;
#endif
@ -161,7 +161,7 @@ static void acpi_init(struct device *dev)
(on*12)+(on>>1),(on&1)*5);
}
#if CONFIG_HAVE_ACPI_TABLES
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
pm_base = pci_read_config16(dev, 0x58) & 0xff00;
printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
#endif

2
src/southbridge/amd/amd8111/lpc.c
View File

@ -129,7 +129,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static void southbridge_acpi_fill_ssdt_generator(device_t device) {
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
amd_generate_powernow(pm_base + 0x10, 6, 1);
acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
#endif

2
src/southbridge/amd/cimx/sb700/Platform.h
View File

@ -59,7 +59,7 @@ void TraceCode ( UINT32 Level, UINT32 Code);
#ifdef TRACE
#undef TRACE
#endif
#if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
#if IS_ENABLED(CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL)
#define TRACE(Arguments) printk Arguments
#else
#define TRACE(Arguments) do {} while (0)

5
src/southbridge/amd/cimx/sb800/SBPLATFORM.h
View File

@ -49,7 +49,7 @@ typedef union _PCI_ADDR {
#endif
#define FIXUP_PTR(ptr) ptr
#if CONFIG_SB800_IMC_FWM
#if IS_ENABLED(CONFIG_SB800_IMC_FWM)
#define IMC_ENABLE_OVER_WRITE 0x01
#endif
@ -153,10 +153,7 @@ typedef union _PCI_ADDR {
#define cimFusionMsgCStageDefault FALSE
#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
#if CONFIG_HAVE_ACPI_RESUME
#include <spi-generic.h>
#endif
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5

2
src/southbridge/amd/cimx/sb800/bootblock.c
View File

@ -99,7 +99,7 @@ static void enable_clocks(void)
// change twice.
reg32 = *acpi_mmio;
reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)
#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK
#if !IS_ENABLED(CONFIG_SUPERIO_WANTS_14MHZ_CLOCK)
reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz
#endif
*acpi_mmio = reg32;

6
src/southbridge/amd/cimx/sb800/late.c
View File

@ -372,7 +372,7 @@ static void sb800_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
clear_ioapic(VIO_APIC_VADDR);
#if CONFIG_CPU_AMD_AGESA
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
#else
@ -406,9 +406,9 @@ static void sb800_enable(device_t dev)
case (0x14 << 3) | 3: /* 0:14:3 LPC */
/* Initialize the fans */
#if CONFIG_SB800_IMC_FAN_CONTROL
#if IS_ENABLED(CONFIG_SB800_IMC_FAN_CONTROL)
init_sb800_IMC_fans(dev);
#elif CONFIG_SB800_MANUAL_FAN_CONTROL
#elif IS_ENABLED(CONFIG_SB800_MANUAL_FAN_CONTROL)
init_sb800_MANUAL_fans(dev);
#endif
break;

4
src/southbridge/amd/cimx/sb900/early.c
View File

@ -96,7 +96,7 @@ void sb_before_pci_init(void)
void sb_After_Pci_Init(void)
{
#if !CONFIG_BOARD_AMD_DINAR
#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
AMDSBCFG sb_early_cfg;
printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
@ -128,7 +128,7 @@ void sb_Mid_Post_Init(void)
void sb_Late_Post(void)
{
#if !CONFIG_BOARD_AMD_DINAR
#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
AMDSBCFG sb_early_cfg;
u8 data;

2
src/southbridge/amd/cs5536/early_setup.c
View File

@ -88,7 +88,7 @@ static void cs5536_setup_iobase(void)
static void cs5536_setup_power_button(void)
{
#if CONFIG_ENABLE_POWER_BUTTON
#if IS_ENABLED(CONFIG_ENABLE_POWER_BUTTON)
outl(0x40020000, PMS_IO_BASE + 0x40);
#endif

2
src/southbridge/amd/cs5536/pirq.c
View File

@ -19,7 +19,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1)
#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)
void pirq_assign_irqs(const unsigned char pIntAtoD[4])
{
device_t pdev;

2
src/southbridge/amd/pi/hudson/acpi/fch.asl
View File

@ -51,7 +51,7 @@ Device(SBUS) {
#include "usb.asl"
/* 0:14.2 - HD Audio */
#if !CONFIG_SOUTHBRIDGE_AMD_PI_KERN
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#include "audio.asl"
#endif

2
src/southbridge/amd/pi/hudson/acpi/sleepstates.asl
View File

@ -23,7 +23,7 @@ If (LAnd(SSFG, 0x01)) {
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
#if CONFIG_HAVE_ACPI_RESUME
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}

6
src/southbridge/amd/pi/hudson/acpi/usb.asl
View File

@ -50,7 +50,8 @@ Device(UOH6) {
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \
!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
/* 0:14.5 - OHCI */
Device(UEH1) {
Name(_ADR, 0x00140005)
@ -64,7 +65,8 @@ Device(XHC0) {
Name(_PRW, Package() {0x0B, 4})
} /* end XHC0 */
#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \
!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
/* 0:10.1 - XHCI 1*/
Device(XHC1) {
Name(_ADR, 0x00100001)

2
src/southbridge/amd/pi/hudson/fadt.c
View File

@ -25,7 +25,7 @@
#include "hudson.h"
#include "smi.h"
#if CONFIG_HUDSON_LEGACY_FREE
#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
#else
#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)

2
src/southbridge/amd/rs690/cmn.c
View File

@ -308,7 +308,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
void rs690_set_tom(device_t nb_dev)
{
/* set TOM */
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
pci_write_config32(nb_dev, 0x90, uma_memory_base);
nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
#else

8
src/southbridge/amd/rs690/ht.c
View File

@ -24,7 +24,7 @@
static void ht_dev_set_resources(device_t dev)
{
#if CONFIG_EXT_CONF_SUPPORT
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
unsigned reg;
device_t k8_f1;
resource_t rbase, rend;
@ -83,7 +83,7 @@ static void ht_dev_set_resources(device_t dev)
unsigned long acpi_fill_mcfg(unsigned long current)
{
#if CONFIG_EXT_CONF_SUPPORT
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
struct resource *res;
resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default
@ -100,7 +100,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
static void ht_dev_read_resources(device_t dev)
{
#if CONFIG_EXT_CONF_SUPPORT
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
struct resource *res;
printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
@ -109,7 +109,7 @@ static void ht_dev_read_resources(device_t dev)
pci_dev_read_resources(dev);
#if CONFIG_EXT_CONF_SUPPORT
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
/* Add an MMCONFIG resource. */
res = new_resource(dev, 0x1C);
res->base = EXT_CONF_BASE_ADDRESS;

2
src/southbridge/amd/rs780/cmn.c
View File

@ -349,7 +349,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
void rs780_set_tom(device_t nb_dev)
{
/* set TOM */
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
pci_write_config32(nb_dev, 0x90, uma_memory_base);
//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
#else

10
src/southbridge/amd/rs780/early_setup.c
View File

@ -97,7 +97,7 @@ static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
}
}
/* family 10 only, for reg > 0xFF */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,
u32 mask, u32 val)
{
@ -143,7 +143,7 @@ static u8 is_famly10(void)
return (cpuid_eax(1) & 0xff00000) != 0;
}
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
static u8 l3_cache(void)
{
return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
@ -242,7 +242,7 @@ static void rs780_htinit(void)
} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
/* HT3 mode, RPR 8.4.3 */
set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
@ -282,7 +282,7 @@ static void rs780_htinit(void)
}
}
#if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10
#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
/*******************************************************
* Optimize k8 with UMA.
* See BKDG_NPT_0F guide for details.
@ -338,7 +338,7 @@ static void k8_optimization(void)
#define k8_optimization() do {} while (0)
#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
static void fam10_optimization(void)
{
pci_devfn_t cpu_f0, cpu_f2, cpu_f3;

10
src/southbridge/amd/rs780/gfx.c
View File

@ -382,7 +382,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* GFX_InitFBAccess finished. */
#if CONFIG_GFXUMA /* for UMA mode. */
#if IS_ENABLED(CONFIG_GFXUMA) /* for UMA mode. */
/* GFX_StartMC. */
set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
@ -444,7 +444,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
vgainfo.sHeader.ucTableFormatRevision = 1;
vgainfo.sHeader.ucTableContentRevision = 2;
#if !CONFIG_GFXUMA /* SP mode. */
#if !IS_ENABLED(CONFIG_GFXUMA) /* SP mode. */
// Side port support is incomplete, do not use it
// These parameters must match the motherboard
vgainfo.ulBootUpSidePortClock = 667*100;
@ -629,7 +629,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Transfer the Table to VBIOS. */
pointer = (u32 *)&vgainfo;
for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
#else
*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
@ -758,7 +758,7 @@ static void rs780_internal_gfx_enable(device_t dev)
device_t nb_dev = dev_find_slot(0, 0);
msr_t sysmem;
#if !CONFIG_GFXUMA
#if !IS_ENABLED(CONFIG_GFXUMA)
u32 FB_Start, FB_End;
#endif
@ -801,7 +801,7 @@ static void rs780_internal_gfx_enable(device_t dev)
set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
/* GFX_InitUMA. */
/* Copy CPU DDR Controller to NB MC. */
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));

2
src/southbridge/amd/rs780/rs780.c
View File

@ -206,7 +206,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
/* Program Straps. */
romstrap2 = 1 << 26; // enables audio function
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
// bits 7-9: aperture size
// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;

8
src/southbridge/amd/sb700/early_setup.c
View File

@ -152,7 +152,7 @@ void sb7xx_51xx_lpc_init(void)
reg32 |= 1 << 20;
pci_write_config32(dev, 0x64, reg32);
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
post_code(0x66);
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
reg8 = pci_read_config8(dev, 0xBB);
@ -166,7 +166,7 @@ void sb7xx_51xx_lpc_init(void)
// XXX Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG_TTYS0_BASE == 0x2f8
reg8 |= 1 << 7;
#endif
@ -532,7 +532,7 @@ static void sb700_devices_por_init(void)
pci_write_config8(dev, 0x50, 0x01);
if (!sata_ahci_mode){
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* SP5100 default SATA mode is RAID5 MODE */
dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0);
@ -688,7 +688,7 @@ static void sb700_pmio_por_init(void)
byte |= 0xc0;
pmio_write(0xbb, byte);
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* RPR 2.26 Alter CPU reset timing */
byte = pmio_read(0xb2);
byte |= 0x1 << 2; /* Enable CPU reset timing option */

4
src/southbridge/amd/sb700/lpc.c
View File

@ -47,7 +47,7 @@ static void lpc_init(device_t dev)
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT)
printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
#else
isa_dma_init();
@ -68,7 +68,7 @@ static void lpc_init(device_t dev)
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* Disable FlowContrl, Always service the request from Host
* whenever there is a request from Host pending
*/

2
src/southbridge/amd/sb700/sata.c
View File

@ -350,7 +350,7 @@ static void sata_init(struct device *dev)
byte |= 7 << 0;
pci_write_config8(dev, 0x4, byte);
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* Master Latency Timer */
pci_write_config32(dev, 0xC, 0x00004000);
#endif

2
src/southbridge/amd/sb700/sb700.c
View File

@ -222,7 +222,7 @@ void sb7xx_51xx_enable(device_t dev)
}
}
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
struct chip_operations southbridge_amd_sb700_ops = {
CHIP_NAME("ATI SP5100")
.enable_dev = sb7xx_51xx_enable,

2
src/southbridge/amd/sb700/usb.c
View File

@ -181,7 +181,7 @@ static void usb_init2(struct device *dev)
dword |= 1 << 8;
dword &= ~(1 << 27); /* 6.23 */
}
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* SP5100 Erratum 36 */
dword &= ~(1 << 26);
if (!ehci_async_data_cache)

9
src/southbridge/amd/sr5650/early_setup.c
View File

@ -50,7 +50,8 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
/* family 10 only, for reg > 0xFF */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
u32 val)
{
@ -221,7 +222,8 @@ void sr5650_htinit(void)
/* Enable Protocol checker */
set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
/* HT3 mode, RPR 5.4.3 */
set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
@ -299,7 +301,8 @@ void sr5650_htinit_dect_and_enable_isochronous_link(void)
}
}
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
void fam10_optimization(void)
{
device_t cpu_f0, cpu_f2, cpu_f3;