security/intel/txt: Get addr bits at runtime
This removes the need for a Kconfig value. Change-Id: Ia9f39aa1c7fb9a64c2e5412bac6e2600b222a635 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -3,8 +3,6 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1)
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/*
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* Configure the MTRRs to cache the BIOS ACM. No general-purpose
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* registers are preserved. Inputs are taken from SSE registers:
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@ -16,6 +14,16 @@
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*/
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.macro SET_UP_MTRRS_FOR_BIOS_ACM
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/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
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movl $0x80000008, %eax
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cpuid
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movb %al, %cl
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sub $32, %cl
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movl $1, %edx
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shl %cl, %edx
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subl $1, %edx
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movl %edx, %edi /* %edi contains the MTRR_HIGH_MASK */
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/* Get the number of variable MTRRs */
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movl $(MTRR_CAP_MSR), %ecx
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rdmsr
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@ -56,7 +64,7 @@ body_allocate_var_mtrrs:
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movd %eax, %xmm1
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/* Program MTRR mask */
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movl MTRR_HIGH_MASK, %edx
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movl %edi, %edx
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xorl %eax, %eax
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subl %ebx, %eax /* %eax = 4GIB - size to cache */
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orl $(MTRR_PHYS_MASK_VALID), %eax
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@ -6,8 +6,6 @@
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#include "getsec_mtrr_setup.inc"
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#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1)
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#define NO_EVICT_MODE 0x2e0
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.align 4
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