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mainboard/amd/serengeti_cheetah: Use tabs for indents 

Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16817
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS 2016-09-29 19:57:09 +02:00 committed by Kyösti Mälkki
parent 75b2237473
commit 08449eb583
2 changed files with 65 additions and 65 deletions
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18
src/mainboard/amd/serengeti_cheetah/mb_sysconf.h
View File

@ -22,18 +22,18 @@ struct mb_sysconf_t {
unsigned char bus_8111_0;
unsigned char bus_8111_1;
unsigned char bus_8132a[7][3];
unsigned char bus_8132a[7][3];
unsigned char bus_8151[7][2];
unsigned char bus_8151[7][2];
unsigned apicid_8111;
unsigned apicid_8132_1;
unsigned apicid_8132_2;
unsigned apicid_8132a[7][2];
unsigned apicid_8111;
unsigned apicid_8132_1;
unsigned apicid_8132_2;
unsigned apicid_8132a[7][2];
unsigned sbdn3;
unsigned sbdn3a[7];
unsigned sbdn5[7];
unsigned sbdn3;
unsigned sbdn3a[7];
unsigned sbdn5[7];
};

112
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -38,8 +38,8 @@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@ -47,20 +47,20 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
i = 2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
} while ((ret != 0) && (i-->0));
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
i = 2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
} while ((ret != 0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0);
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdk8/amdk8.h>
@ -83,32 +83,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
//first node
RC0|DIMM0, RC0|DIMM2, 0, 0,
RC0|DIMM1, RC0|DIMM3, 0, 0,
RC0|DIMM0, RC0|DIMM2, 0, 0,
RC0|DIMM1, RC0|DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC2|DIMM0, RC2|DIMM2, 0, 0,
RC2|DIMM1, RC2|DIMM3, 0, 0,
// four node
RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
// third node
RC2|DIMM0, RC2|DIMM2, 0, 0,
RC2|DIMM1, RC2|DIMM3, 0, 0,
// four node
RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
#endif
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset;
unsigned bsp_apicid = 0;
int needs_reset;
unsigned bsp_apicid = 0;
#if CONFIG_SET_FIDVID
struct cpuid_result cpuid1;
#endif
if (bist == 0)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@ -121,35 +121,35 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_mb_resource_map();
setup_mb_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
#if CONFIG_SET_FIDVID
@ -158,23 +158,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) {
{
{
/* Read FIDVID_STATUS */
msr_t msr;
msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
msr_t msr;
msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
// show final fid and vid
{
msr_t msr;
msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
@ -185,15 +185,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
#endif
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
@ -209,20 +209,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synchronize FID/VID
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synchronize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
print_pci_devices();
print_pci_devices();
#endif
#if 0
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}