soc/amd/common: Update AcpiMmio comments
Document the AcpiMmio individual blocks better. This is in response to a request in gerrit for 69486cac7: Create AcpiMmio functionality from stoneyridge Correct comments that were inadvertently left in place from older patches. Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
59fbe89530
commit
08462ce590
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@ -214,7 +214,7 @@ void acpi_write32(u8 reg, u32 value)
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write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
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}
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/* asf read/write - access registers at 0xfed80900 - not currently used */
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/* asf read/write - access registers at 0xfed80900 */
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u8 asf_read8(u8 reg)
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{
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@ -236,7 +236,7 @@ void asf_write16(u8 reg, u16 value)
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write16((void *)(ACPIMMIO_ASF_BASE + reg), value);
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}
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/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */
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/* smbus read/write - access registers at 0xfed80a00 */
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u8 smbus_read8(u8 reg)
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{
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@ -364,9 +364,9 @@ void xhci_pm_write32(uint8_t reg, uint32_t value)
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write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
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}
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/* acdc_tmr read/write - access registers at 0xfed81d00 */
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/* acdc_tmr read/write - access registers at 0xfed81d00 - not currently used */
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/* aoac read/write - access registers at 0xfed81e00 - not currently used */
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/* aoac read/write - access registers at 0xfed81e00 */
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u8 aoac_read8(u8 reg)
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{
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@ -18,81 +18,187 @@
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#ifndef __AMDBLOCKS_ACPIMMIO_H__
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#define __AMDBLOCKS_ACPIMMIO_H__
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/*
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* The following AcpiMmio register block mapping represents definitions
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* that have been documented in AMD publications. All blocks aren't
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* implemented in all products, so the caller should be careful not to
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* inadvertently access a non-existent block. The definitions within
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* each block are also subject to change across products. Please refer
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* to the appropriate RRG, the BKDG, or PPR for the product.
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*
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* The base address is configurable in older products, but defaults to
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* 0xfed80000. The address is fixed at 0xfed80000 in newer products.
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*
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* +---------------------------------------------------------------------------+
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* |0x000 SMBus PCI space |
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* | * Dual-mapped to PCI configuration header of D14F0 |
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* +---------------------------------------------------------------------------+
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* |0x100 GPIO configuration registers |
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* | * old style, never implemented with newer style |
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* +---------------------------------------------------------------------------+
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* |0x200 SMI configuration registers |
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* +---------------------------------------------------------------------------+
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* |0x300 Power Management registers |
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* | * Dual-mapped via IO Index/Data 0xcd6/0xcd7 (byte access only) |
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* +---------------------------------------------------------------------------+
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* |0x400 Power Management 2 registers |
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* +---------------------------------------------------------------------------+
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* |0x500 BIOS RAM |
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* | * General-purpose storage in S3 domain |
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* | * Byte access only |
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* +---------------------------------------------------------------------------+
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* |0x600 CMOS RAM |
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* | * Dual-mapped to storage at Alt RTC Index/Data (0x72/0x73) |
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* | * Byte access only |
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* +---------------------------------------------------------------------------+
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* |0x700 CMOS |
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* | * Dual-mapped to storage at RTC Index/Data (0x70/0x71) |
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* | * Byte access only |
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* +---------------------------------------------------------------------------+
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* |0x800 Standard ACPI registers |
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* | * Dual-mapped to I/O ACPI registers |
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* +---------------------------------------------------------------------------+
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* |0x900 ASF controller registers |
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* | * Dual-mapped to I/O ASF controller registers |
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* +---------------------------------------------------------------------------+
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* |0xa00 SMBus controller registers |
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* | * Dual-mapped to I/O SMBus controller registers |
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* +---------------------------------------------------------------------------+
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* |0xb00 WDT registers |
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* | * Dual-mapped to WDT registers, typ. enabled at 0xfeb00000 |
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* +---------------------------------------------------------------------------+
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* |0xc00 HPET registers |
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* | * Dual-mapped to HPET registers, typ. enabled at 0xfed00000 |
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* +---------------------------------------------------------------------------+
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* |0xd00 MUX configuration registers for GPIO signals |
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* +---------------------------------------------------------------------------+
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* |0xe00 Miscellaneous registers |
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* +---------------------------------------------------------------------------+
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* |0x1000 Serial debug bus |
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* +---------------------------------------------------------------------------+
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* |0x1400 DP-VGA |
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* +---------------------------------------------------------------------------+
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* |0x1500 GPIO configuration registers bank 0 |
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* | * new style, never implemented with older style |
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* +---------------------------------------------------------------------------+
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* |0x1600 GPIO configuration registers bank 1 |
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* | * new style, never implemented with older style |
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* +---------------------------------------------------------------------------+
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* |0x1700 GPIO configuration registers bank 2 |
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* | * new style, never implemented with older style |
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* +---------------------------------------------------------------------------+
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* |0x1c00 xHCI Power Management registers |
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* +---------------------------------------------------------------------------+
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* |0x1d00 Wake device (AC DC timer) |
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* +---------------------------------------------------------------------------+
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* |0x1e00 Always On Always Connect registers |
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* +---------------------------------------------------------------------------+
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*/
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/* Enable the AcpiMmio range at 0xfed80000 */
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void enable_acpimmio_decode(void);
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/* Access PM registers using IO cycles */
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uint8_t pm_io_read8(uint8_t reg);
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uint16_t pm_io_read16(uint8_t reg);
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uint32_t pm_io_read32(uint8_t reg);
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void pm_io_write8(uint8_t reg, uint8_t value);
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void pm_io_write16(uint8_t reg, uint16_t value);
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void pm_io_write32(uint8_t reg, uint32_t value);
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/* Access SMI registers at 0xfed80100 */
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uint8_t smi_read8(uint8_t reg);
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uint16_t smi_read16(uint8_t reg);
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uint32_t smi_read32(uint8_t reg);
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void smi_write8(uint8_t reg, uint8_t value);
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void smi_write16(uint8_t reg, uint16_t value);
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void smi_write32(uint8_t reg, uint32_t value);
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/* Access Power Management registers at 0xfed80300 */
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uint8_t pm_read8(uint8_t reg);
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uint16_t pm_read16(uint8_t reg);
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uint32_t pm_read32(uint8_t reg);
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void pm_write8(uint8_t reg, uint8_t value);
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void pm_write16(uint8_t reg, uint16_t value);
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void pm_write32(uint8_t reg, uint32_t value);
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/* Access Power Management 2 registers at 0xfed80400 */
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uint8_t pm2_read8(uint8_t reg);
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uint16_t pm2_read16(uint8_t reg);
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uint32_t pm2_read32(uint8_t reg);
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void pm2_write8(uint8_t reg, uint8_t value);
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void pm2_write16(uint8_t reg, uint16_t value);
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void pm2_write32(uint8_t reg, uint32_t value);
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/* Access BIOS RAM storage at 0xfed80500 */
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uint8_t biosram_read8(uint8_t reg);
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uint16_t biosram_read16(uint8_t reg);
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uint32_t biosram_read32(uint8_t reg);
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void biosram_write8(uint8_t reg, uint8_t value);
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void biosram_write16(uint8_t reg, uint16_t value);
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void biosram_write32(uint8_t reg, uint32_t value);
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/* Access ACPI registers at 0xfed80800 */
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uint8_t acpi_read8(uint8_t reg);
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uint16_t acpi_read16(uint8_t reg);
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uint32_t acpi_read32(uint8_t reg);
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void acpi_write8(uint8_t reg, uint8_t value);
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void acpi_write16(uint8_t reg, uint16_t value);
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void acpi_write32(uint8_t reg, uint32_t value);
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/* Access ASF controller registers at 0xfed80900 */
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uint8_t asf_read8(uint8_t reg);
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uint16_t asf_read16(uint8_t reg);
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void asf_write8(uint8_t reg, uint8_t value);
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void asf_write16(uint8_t reg, uint16_t value);
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/* Access SMBus controller registers at 0xfed80a00 */
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uint8_t smbus_read8(uint8_t reg);
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uint16_t smbus_read16(uint8_t reg);
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void smbus_write8(uint8_t reg, uint8_t value);
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void smbus_write16(uint8_t reg, uint16_t value);
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/* Access WDT registers at 0xfed80b00 */
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uint8_t wdt_read8(uint8_t reg);
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uint16_t wdt_read16(uint8_t reg);
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uint32_t wdt_read32(uint8_t reg);
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void wdt_write8(uint8_t reg, uint8_t value);
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void wdt_write16(uint8_t reg, uint16_t value);
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void wdt_write32(uint8_t reg, uint32_t value);
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/* Access HPET registers at 0xfed80c00 */
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uint8_t hpet_read8(uint8_t reg);
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uint16_t hpet_read16(uint8_t reg);
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uint32_t hpet_read32(uint8_t reg);
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void hpet_write8(uint8_t reg, uint8_t value);
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void hpet_write16(uint8_t reg, uint16_t value);
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void hpet_write32(uint8_t reg, uint32_t value);
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/* Access GPIO MUX registers at 0xfed80d00 */
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uint8_t iomux_read8(uint8_t reg);
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uint16_t iomux_read16(uint8_t reg);
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uint32_t iomux_read32(uint8_t reg);
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void iomux_write8(uint8_t reg, uint8_t value);
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void iomux_write16(uint8_t reg, uint16_t value);
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void iomux_write32(uint8_t reg, uint32_t value);
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/* Access Miscellaneous registers at 0xfed80e00 */
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uint8_t misc_read8(uint8_t reg);
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uint16_t misc_read16(uint8_t reg);
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uint32_t misc_read32(uint8_t reg);
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void misc_write8(uint8_t reg, uint8_t value);
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void misc_write16(uint8_t reg, uint16_t value);
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void misc_write32(uint8_t reg, uint32_t value);
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/* Access xHCI Power Management registers at 0xfed81c00 */
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uint8_t xhci_pm_read8(uint8_t reg);
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uint16_t xhci_pm_read16(uint8_t reg);
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uint32_t xhci_pm_read32(uint8_t reg);
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void xhci_pm_write8(uint8_t reg, uint8_t value);
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void xhci_pm_write16(uint8_t reg, uint16_t value);
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void xhci_pm_write32(uint8_t reg, uint32_t value);
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/* Access Always On Always Connect registers at 0xfed81e00 */
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uint8_t aoac_read8(uint8_t reg);
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void aoac_write8(uint8_t reg, uint8_t value);
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