From 08529918fcc11fde87e3a78dab0fe73e72b04de5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Dec 2022 16:28:11 +0530 Subject: [PATCH] mb/google/rex: Add support for WWAN over USB3 This patch connects USB3_PCH_*_WWAN_* to USB32_2 as per Proto 1 schematics dated 12/14/2022. TEST=Able to build Google/Rex. Change-Id: Ie04c79ff5c231527e3d5f63a5cc553ec39c46914 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/70749 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Ivy Jian Reviewed-by: Kapil Porwal --- src/mainboard/google/rex/variants/rex0/overridetree.cb | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 0ef8fe221f..b02999fe55 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -38,7 +38,7 @@ chip soc/intel/meteorlake register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" @@ -213,6 +213,13 @@ chip soc/intel/meteorlake register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe CELLULAR CELLULAR_USB + end + end end end end