baytrail: Add IOSF functions for USBPHY and USHPHY
These are needed for USB2 and USB3 PHY init sequences. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4916 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -64,6 +64,10 @@ uint32_t iosf_dunit_ch0_read(int reg);
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uint32_t iosf_dunit_ch1_read(int reg);
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uint32_t iosf_punit_read(int reg);
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void iosf_punit_write(int reg, uint32_t val);
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uint32_t iosf_usbphy_read(int reg);
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void iosf_usbphy_write(int reg, uint32_t val);
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uint32_t iosf_ushphy_read(int reg);
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void iosf_ushphy_write(int reg, uint32_t val);
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/* IOSF ports. */
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#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */
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@ -76,6 +80,7 @@ void iosf_punit_write(int reg, uint32_t val);
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#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */
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#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */
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#define IOSF_PORT_USBPHY 0x43 /* USB PHY */
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#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */
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#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */
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#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */
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@ -96,6 +101,8 @@ void iosf_punit_write(int reg, uint32_t val);
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#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1)
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#define IOSF_OP_READ_USBPHY 0x06
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#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1)
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#define IOSF_OP_READ_USHPHY 0x06
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#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1)
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#define IOSF_OP_READ_SATAPHY 0x00
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#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1)
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#define IOSF_OP_READ_PCIEPHY 0x00
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@ -121,3 +121,47 @@ void iosf_punit_write(int reg, uint32_t val)
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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}
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uint32_t iosf_usbphy_read(int reg)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) |
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IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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return read_iosf_reg(MDR_REG);
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}
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void iosf_usbphy_write(int reg, uint32_t val)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) |
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IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MDR_REG, val);
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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}
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uint32_t iosf_ushphy_read(int reg)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) |
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IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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return read_iosf_reg(MDR_REG);
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}
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void iosf_ushphy_write(int reg, uint32_t val)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) |
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IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MDR_REG, val);
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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}
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