sb/intel: Move 'smbus.asl' to common place
Change-Id: Ia5b148c54224269bda98afe7c8a2c22c10a3bf56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
ca64305152
commit
085ab5a347
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@ -251,7 +251,7 @@ Scope(\)
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#include "sata.asl"
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// SMBus 0:1f.3
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#include "smbus.asl"
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#include <southbridge/intel/common/acpi/smbus.asl>
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Method (_OSC, 4)
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{
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@ -1,236 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Intel SMBus Controller 0:1f.3
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Device (SBUS)
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{
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Name (_ADR, 0x001f0003)
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#ifdef ENABLE_SMBUS_METHODS
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OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
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Field(SMBP, DWordAcc, NoLock, Preserve)
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{
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Offset(0x40),
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, 2,
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I2CE, 1
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}
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OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20)
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Field (SMBI, ByteAcc, NoLock, Preserve)
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{
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HSTS, 8, // Host Status
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, 8,
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HCNT, 8, // Host Control
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HCMD, 8, // Host Command
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TXSA, 8, // Transmit Slave Address
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DAT0, 8, // Host Data 0
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DAT1, 8, // Host Data 1
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HBDB, 8, // Host Block Data Byte
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PECK, 8, // Packet Error Check
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RXSA, 8, // Receive Slave Address
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RXDA, 16, // Receive Slave Data
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AUXS, 8, // Auxiliary Status
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AUXC, 8, // Auxiliary Control
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SLPC, 8, // SMLink Pin Control
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SBPC, 8, // SMBus Pin Control
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SSTS, 8, // Slave Status
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SCMD, 8, // Slave Command
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NADR, 8, // Notify Device Address
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NDLB, 8, // Notify Data Low Byte
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NDLH, 8, // Notify Data High Byte
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}
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// Kill all SMBus communication
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Method (KILL, 0, Serialized)
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{
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Or (HCNT, 0x02, HCNT) // Send Kill
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Or (HSTS, 0xff, HSTS) // Clean Status
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}
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// Check if last operation completed
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// return Failure = 0, Success = 1
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Method (CMPL, 0, Serialized)
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{
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Store (4000, Local0) // Timeout 200ms in 50us steps
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While (Local0) {
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If (And(HSTS, 0x02)) { // Completion Status?
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Return (1) // Operation Completed
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} Else {
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Stall (50)
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Decrement (Local0)
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If (LEqual(Local0, 0)) {
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KILL()
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}
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}
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}
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Return (0) // Failure
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}
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// Wait for SMBus to become ready
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Method (SRDY, 0, Serialized)
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{
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Store (200, Local0) // Timeout 200ms
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While (Local0) {
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If (And(HSTS, 0x40)) { // IN_USE?
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Sleep(1) // Wait 1ms
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Decrement(Local0) // timeout--
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If (LEqual(Local0, 0)) {
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Return (1)
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}
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} Else {
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Store (0, Local0) // We're ready
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}
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}
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Store (4000, Local0) // Timeout 200ms (50us * 4000)
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While (Local0) {
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If (And (HSTS, 0x01)) { // Host Busy?
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Stall(50) // Wait 50us
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Decrement(Local0) // timeout--
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If (LEqual(Local0, 0)) {
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KILL()
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}
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} Else {
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Return (0) // Success
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}
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}
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Return (1) // Failure
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}
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// SMBus Send Byte
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// Arg0: Address
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// Arg1: Data
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// Return: 1 = Success, 0=Failure
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Method (SSXB, 2, Serialized)
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{
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// Is the SMBus Controller Ready?
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If (SRDY()) {
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Return (0)
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}
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// Send Byte
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Store (0, I2CE) // SMBus Enable
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Store (0xbf, HSTS)
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Store (Arg0, TXSA) // Write Address
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Store (Arg1, HCMD) // Write Data
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Store (0x48, HCNT) // Start + Byte Data Protocol
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If (CMPL()) {
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Or (HSTS, 0xff, HSTS) // Clean up
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Return (1) // Success
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}
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Return (0)
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}
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// SMBus Receive Byte
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// Arg0: Address
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// Return: 0xffff = Failure, Data (8bit) = Success
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Method (SRXB, 2, Serialized)
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{
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// Is the SMBus Controller Ready?
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If (SRDY()) {
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Return (0xffff)
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}
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// Receive Byte
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Store (0, I2CE) // SMBus Enable
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Store (0xbf, HSTS)
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Store (Or (Arg0, 1), TXSA) // Write Address
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Store (0x44, HCNT) // Start
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If (CMPL()) {
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Or (HSTS, 0xff, HSTS) // Clean up
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Return (DAT0) // Success
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}
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Return (0xffff)
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}
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// SMBus Write Byte
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// Arg0: Address
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// Arg1: Command
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// Arg2: Data
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// Return: 1 = Success, 0=Failure
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Method (SWRB, 3, Serialized)
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{
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// Is the SMBus Controller Ready?
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If (SRDY()) {
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Return (0)
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}
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// Send Byte
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Store (0, I2CE) // SMBus Enable
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Store (0xbf, HSTS)
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Store (Arg0, TXSA) // Write Address
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Store (Arg1, HCMD) // Write Command
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Store (Arg2, DAT0) // Write Data
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Store (0x48, HCNT) // Start + Byte Protocol
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If (CMPL()) {
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Or (HSTS, 0xff, HSTS) // Clean up
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Return (1) // Success
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}
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Return (0)
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}
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// SMBus Read Byte
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// Arg0: Address
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// Arg1: Command
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// Return: 0xffff = Failure, Data (8bit) = Success
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Method (SRDB, 2, Serialized)
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{
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// Is the SMBus Controller Ready?
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If (SRDY()) {
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Return (0xffff)
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}
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// Receive Byte
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Store (0, I2CE) // SMBus Enable
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Store (0xbf, HSTS)
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Store (Or (Arg0, 1), TXSA) // Write Address
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Store (Arg1, HCMD) // Command
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Store (0x48, HCNT) // Start
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If (CMPL()) {
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Or (HSTS, 0xff, HSTS) // Clean up
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Return (DAT0) // Success
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}
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Return (0xffff)
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}
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#endif
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}
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@ -249,7 +249,7 @@ Scope(\)
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#include "sata.asl"
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// SMBus 0:1f.3
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#include "smbus.asl"
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#include <southbridge/intel/common/acpi/smbus.asl>
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// IRQ routing for each PCI device
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#include "irqroute.asl"
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@ -186,4 +186,4 @@ Scope(\)
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#include "sata.asl"
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// SMBus
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#include "smbus.asl"
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#include <southbridge/intel/common/acpi/smbus.asl>
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@ -1,236 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Intel SMBus Controller 0:1f.3
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Device (SBUS)
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{
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Name (_ADR, 0x001f0003)
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#ifdef ENABLE_SMBUS_METHODS
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OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
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Field(SMBP, DWordAcc, NoLock, Preserve)
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{
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Offset(0x40),
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, 2,
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I2CE, 1
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}
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OperationRegion (SMBI, SystemIO, 0x400, 0x20)
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Field (SMBI, ByteAcc, NoLock, Preserve)
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{
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HSTS, 8, // Host Status
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, 8,
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HCNT, 8, // Host Control
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HCMD, 8, // Host Command
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TXSA, 8, // Transmit Slave Address
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DAT0, 8, // Host Data 0
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DAT1, 8, // Host Data 1
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HBDB, 8, // Host Block Data Byte
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PECK, 8, // Packet Error Check
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RXSA, 8, // Receive Slave Address
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RXDA, 16, // Receive Slave Data
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AUXS, 8, // Auxiliary Status
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AUXC, 8, // Auxiliary Control
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SLPC, 8, // SMLink Pin Control
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SBPC, 8, // SMBus Pin Control
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SSTS, 8, // Slave Status
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SCMD, 8, // Slave Command
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NADR, 8, // Notify Device Address
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NDLB, 8, // Notify Data Low Byte
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NDLH, 8, // Notify Data High Byte
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}
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// Kill all SMBus communication
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Method (KILL, 0, Serialized)
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{
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Or (HCNT, 0x02, HCNT) // Send Kill
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Or (HSTS, 0xff, HSTS) // Clean Status
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}
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// Check if last operation completed
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// return Failure = 0, Success = 1
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Method (CMPL, 0, Serialized)
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{
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Store (4000, Local0) // Timeout 200ms in 50us steps
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While (Local0) {
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If (And(HSTS, 0x02)) { // Completion Status?
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Return (1) // Operation Completed
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} Else {
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Stall (50)
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Decrement (Local0)
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If (LEqual(Local0, 0)) {
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KILL()
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}
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}
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}
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Return (0) // Failure
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}
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// Wait for SMBus to become ready
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Method (SRDY, 0, Serialized)
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{
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Store (200, Local0) // Timeout 200ms
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While (Local0) {
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If (And(HSTS, 0x40)) { // IN_USE?
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Sleep(1) // Wait 1ms
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Decrement(Local0) // timeout--
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If (LEqual(Local0, 0)) {
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Return (1)
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}
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} Else {
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Store (0, Local0) // We're ready
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}
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}
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Store (4000, Local0) // Timeout 200ms (50us * 4000)
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While (Local0) {
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If (And (HSTS, 0x01)) { // Host Busy?
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Stall(50) // Wait 50us
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Decrement(Local0) // timeout--
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If (LEqual(Local0, 0)) {
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KILL()
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}
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} Else {
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Return (0) // Success
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}
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}
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Return (1) // Failure
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}
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// SMBus Send Byte
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// Arg0: Address
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// Arg1: Data
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// Return: 1 = Success, 0=Failure
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Method (SSXB, 2, Serialized)
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{
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// Is the SMBus Controller Ready?
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If (SRDY()) {
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Return (0)
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}
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// Send Byte
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Store (0, I2CE) // SMBus Enable
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Store (0xbf, HSTS)
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Store (Arg0, TXSA) // Write Address
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Store (Arg1, HCMD) // Write Data
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Store (0x48, HCNT) // Start + Byte Data Protocol
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If (CMPL()) {
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Or (HSTS, 0xff, HSTS) // Clean up
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Return (1) // Success
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}
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Return (0)
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}
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// SMBus Receive Byte
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// Arg0: Address
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// Return: 0xffff = Failure, Data (8bit) = Success
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Method (SRXB, 2, Serialized)
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{
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// Is the SMBus Controller Ready?
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If (SRDY()) {
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Return (0xffff)
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}
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// Receive Byte
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Store (0, I2CE) // SMBus Enable
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||||
Store (0xbf, HSTS)
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Store (Or (Arg0, 1), TXSA) // Write Address
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||||
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Store (0x44, HCNT) // Start
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||||
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If (CMPL()) {
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Or (HSTS, 0xff, HSTS) // Clean up
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Return (DAT0) // Success
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}
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Return (0xffff)
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}
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||||
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||||
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||||
// SMBus Write Byte
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// Arg0: Address
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// Arg1: Command
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||||
// Arg2: Data
|
||||
// Return: 1 = Success, 0=Failure
|
||||
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Method (SWRB, 3, Serialized)
|
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{
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// Is the SMBus Controller Ready?
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If (SRDY()) {
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Return (0)
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}
|
||||
|
||||
// Send Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Arg0, TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Write Command
|
||||
Store (Arg2, DAT0) // Write Data
|
||||
|
||||
Store (0x48, HCNT) // Start + Byte Protocol
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (1) // Success
|
||||
}
|
||||
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Read Byte
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// Arg0: Address
|
||||
// Arg1: Command
|
||||
// Return: 0xffff = Failure, Data (8bit) = Success
|
||||
|
||||
Method (SRDB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
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Return (0xffff)
|
||||
}
|
||||
|
||||
// Receive Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Or (Arg0, 1), TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Command
|
||||
|
||||
Store (0x48, HCNT) // Start
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
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||||
Return (DAT0) // Success
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||||
}
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||||
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Return (0xffff)
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}
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#endif
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}
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@ -183,7 +183,7 @@ Scope(\)
|
|||
#include "sata.asl"
|
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|
||||
// SMBus
|
||||
#include "smbus.asl"
|
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#include <southbridge/intel/common/acpi/smbus.asl>
|
||||
|
||||
Method (_OSC, 4)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,236 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// Intel SMBus Controller 0:1f.3
|
||||
|
||||
Device (SBUS)
|
||||
{
|
||||
Name (_ADR, 0x001f0003)
|
||||
|
||||
#ifdef ENABLE_SMBUS_METHODS
|
||||
OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
|
||||
Field(SMBP, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset(0x40),
|
||||
, 2,
|
||||
I2CE, 1
|
||||
}
|
||||
|
||||
OperationRegion (SMBI, SystemIO, 0x400, 0x20)
|
||||
Field (SMBI, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
HSTS, 8, // Host Status
|
||||
, 8,
|
||||
HCNT, 8, // Host Control
|
||||
HCMD, 8, // Host Command
|
||||
TXSA, 8, // Transmit Slave Address
|
||||
DAT0, 8, // Host Data 0
|
||||
DAT1, 8, // Host Data 1
|
||||
HBDB, 8, // Host Block Data Byte
|
||||
PECK, 8, // Packet Error Check
|
||||
RXSA, 8, // Receive Slave Address
|
||||
RXDA, 16, // Receive Slave Data
|
||||
AUXS, 8, // Auxiliary Status
|
||||
AUXC, 8, // Auxiliary Control
|
||||
SLPC, 8, // SMLink Pin Control
|
||||
SBPC, 8, // SMBus Pin Control
|
||||
SSTS, 8, // Slave Status
|
||||
SCMD, 8, // Slave Command
|
||||
NADR, 8, // Notify Device Address
|
||||
NDLB, 8, // Notify Data Low Byte
|
||||
NDLH, 8, // Notify Data High Byte
|
||||
}
|
||||
|
||||
// Kill all SMBus communication
|
||||
Method (KILL, 0, Serialized)
|
||||
{
|
||||
Or (HCNT, 0x02, HCNT) // Send Kill
|
||||
Or (HSTS, 0xff, HSTS) // Clean Status
|
||||
}
|
||||
|
||||
// Check if last operation completed
|
||||
// return Failure = 0, Success = 1
|
||||
Method (CMPL, 0, Serialized)
|
||||
{
|
||||
Store (4000, Local0) // Timeout 200ms in 50us steps
|
||||
While (Local0) {
|
||||
If (And(HSTS, 0x02)) { // Completion Status?
|
||||
Return (1) // Operation Completed
|
||||
} Else {
|
||||
Stall (50)
|
||||
Decrement (Local0)
|
||||
If (LEqual(Local0, 0)) {
|
||||
KILL()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Return (0) // Failure
|
||||
}
|
||||
|
||||
|
||||
// Wait for SMBus to become ready
|
||||
Method (SRDY, 0, Serialized)
|
||||
{
|
||||
Store (200, Local0) // Timeout 200ms
|
||||
While (Local0) {
|
||||
If (And(HSTS, 0x40)) { // IN_USE?
|
||||
Sleep(1) // Wait 1ms
|
||||
Decrement(Local0) // timeout--
|
||||
If (LEqual(Local0, 0)) {
|
||||
Return (1)
|
||||
}
|
||||
} Else {
|
||||
Store (0, Local0) // We're ready
|
||||
}
|
||||
}
|
||||
|
||||
Store (4000, Local0) // Timeout 200ms (50us * 4000)
|
||||
While (Local0) {
|
||||
If (And (HSTS, 0x01)) { // Host Busy?
|
||||
Stall(50) // Wait 50us
|
||||
Decrement(Local0) // timeout--
|
||||
If (LEqual(Local0, 0)) {
|
||||
KILL()
|
||||
}
|
||||
} Else {
|
||||
Return (0) // Success
|
||||
}
|
||||
}
|
||||
|
||||
Return (1) // Failure
|
||||
}
|
||||
|
||||
// SMBus Send Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Data
|
||||
// Return: 1 = Success, 0=Failure
|
||||
|
||||
Method (SSXB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Send Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Arg0, TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Write Data
|
||||
|
||||
Store (0x48, HCNT) // Start + Byte Data Protocol
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (1) // Success
|
||||
}
|
||||
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Receive Byte
|
||||
// Arg0: Address
|
||||
// Return: 0xffff = Failure, Data (8bit) = Success
|
||||
|
||||
Method (SRXB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
// Receive Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Or (Arg0, 1), TXSA) // Write Address
|
||||
|
||||
Store (0x44, HCNT) // Start
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (DAT0) // Success
|
||||
}
|
||||
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Write Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Command
|
||||
// Arg2: Data
|
||||
// Return: 1 = Success, 0=Failure
|
||||
|
||||
Method (SWRB, 3, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Send Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Arg0, TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Write Command
|
||||
Store (Arg2, DAT0) // Write Data
|
||||
|
||||
Store (0x48, HCNT) // Start + Byte Protocol
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (1) // Success
|
||||
}
|
||||
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Read Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Command
|
||||
// Return: 0xffff = Failure, Data (8bit) = Success
|
||||
|
||||
Method (SRDB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
// Receive Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Or (Arg0, 1), TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Command
|
||||
|
||||
Store (0x48, HCNT) // Start
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (DAT0) // Success
|
||||
}
|
||||
|
||||
Return (0xffff)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -184,7 +184,7 @@ Scope(\)
|
|||
#include "sata.asl"
|
||||
|
||||
// SMBus
|
||||
#include "smbus.asl"
|
||||
#include <southbridge/intel/common/acpi/smbus.asl>
|
||||
|
||||
Method (_OSC, 4)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,236 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// Intel SMBus Controller 0:1f.3
|
||||
|
||||
Device (SBUS)
|
||||
{
|
||||
Name (_ADR, 0x001f0003)
|
||||
|
||||
#ifdef ENABLE_SMBUS_METHODS
|
||||
OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
|
||||
Field(SMBP, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset(0x40),
|
||||
, 2,
|
||||
I2CE, 1
|
||||
}
|
||||
|
||||
OperationRegion (SMBI, SystemIO, 0x400, 0x20)
|
||||
Field (SMBI, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
HSTS, 8, // Host Status
|
||||
, 8,
|
||||
HCNT, 8, // Host Control
|
||||
HCMD, 8, // Host Command
|
||||
TXSA, 8, // Transmit Slave Address
|
||||
DAT0, 8, // Host Data 0
|
||||
DAT1, 8, // Host Data 1
|
||||
HBDB, 8, // Host Block Data Byte
|
||||
PECK, 8, // Packet Error Check
|
||||
RXSA, 8, // Receive Slave Address
|
||||
RXDA, 16, // Receive Slave Data
|
||||
AUXS, 8, // Auxiliary Status
|
||||
AUXC, 8, // Auxiliary Control
|
||||
SLPC, 8, // SMLink Pin Control
|
||||
SBPC, 8, // SMBus Pin Control
|
||||
SSTS, 8, // Slave Status
|
||||
SCMD, 8, // Slave Command
|
||||
NADR, 8, // Notify Device Address
|
||||
NDLB, 8, // Notify Data Low Byte
|
||||
NDLH, 8, // Notify Data High Byte
|
||||
}
|
||||
|
||||
// Kill all SMBus communication
|
||||
Method (KILL, 0, Serialized)
|
||||
{
|
||||
Or (HCNT, 0x02, HCNT) // Send Kill
|
||||
Or (HSTS, 0xff, HSTS) // Clean Status
|
||||
}
|
||||
|
||||
// Check if last operation completed
|
||||
// return Failure = 0, Success = 1
|
||||
Method (CMPL, 0, Serialized)
|
||||
{
|
||||
Store (4000, Local0) // Timeout 200ms in 50us steps
|
||||
While (Local0) {
|
||||
If (And(HSTS, 0x02)) { // Completion Status?
|
||||
Return (1) // Operation Completed
|
||||
} Else {
|
||||
Stall (50)
|
||||
Decrement (Local0)
|
||||
If (LEqual(Local0, 0)) {
|
||||
KILL()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Return (0) // Failure
|
||||
}
|
||||
|
||||
|
||||
// Wait for SMBus to become ready
|
||||
Method (SRDY, 0, Serialized)
|
||||
{
|
||||
Store (200, Local0) // Timeout 200ms
|
||||
While (Local0) {
|
||||
If (And(HSTS, 0x40)) { // IN_USE?
|
||||
Sleep(1) // Wait 1ms
|
||||
Decrement(Local0) // timeout--
|
||||
If (LEqual(Local0, 0)) {
|
||||
Return (1)
|
||||
}
|
||||
} Else {
|
||||
Store (0, Local0) // We're ready
|
||||
}
|
||||
}
|
||||
|
||||
Store (4000, Local0) // Timeout 200ms (50us * 4000)
|
||||
While (Local0) {
|
||||
If (And (HSTS, 0x01)) { // Host Busy?
|
||||
Stall(50) // Wait 50us
|
||||
Decrement(Local0) // timeout--
|
||||
If (LEqual(Local0, 0)) {
|
||||
KILL()
|
||||
}
|
||||
} Else {
|
||||
Return (0) // Success
|
||||
}
|
||||
}
|
||||
|
||||
Return (1) // Failure
|
||||
}
|
||||
|
||||
// SMBus Send Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Data
|
||||
// Return: 1 = Success, 0=Failure
|
||||
|
||||
Method (SSXB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Send Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Arg0, TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Write Data
|
||||
|
||||
Store (0x48, HCNT) // Start + Byte Data Protocol
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (1) // Success
|
||||
}
|
||||
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Receive Byte
|
||||
// Arg0: Address
|
||||
// Return: 0xffff = Failure, Data (8bit) = Success
|
||||
|
||||
Method (SRXB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
// Receive Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Or (Arg0, 1), TXSA) // Write Address
|
||||
|
||||
Store (0x44, HCNT) // Start
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (DAT0) // Success
|
||||
}
|
||||
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Write Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Command
|
||||
// Arg2: Data
|
||||
// Return: 1 = Success, 0=Failure
|
||||
|
||||
Method (SWRB, 3, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Send Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Arg0, TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Write Command
|
||||
Store (Arg2, DAT0) // Write Data
|
||||
|
||||
Store (0x48, HCNT) // Start + Byte Protocol
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (1) // Success
|
||||
}
|
||||
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Read Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Command
|
||||
// Return: 0xffff = Failure, Data (8bit) = Success
|
||||
|
||||
Method (SRDB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
// Receive Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Or (Arg0, 1), TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Command
|
||||
|
||||
Store (0x48, HCNT) // Start
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (DAT0) // Success
|
||||
}
|
||||
|
||||
Return (0xffff)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -93,7 +93,7 @@ Scope(\)
|
|||
#include "sata.asl"
|
||||
|
||||
// SMBus 0:1f.3
|
||||
#include "smbus.asl"
|
||||
#include <southbridge/intel/common/acpi/smbus.asl>
|
||||
|
||||
// Serial IO
|
||||
#if CONFIG(INTEL_LYNXPOINT_LP)
|
||||
|
|
|
|||
|
|
@ -1,236 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// Intel SMBus Controller 0:1f.3
|
||||
|
||||
Device (SBUS)
|
||||
{
|
||||
Name (_ADR, 0x001f0003)
|
||||
|
||||
#ifdef ENABLE_SMBUS_METHODS
|
||||
OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
|
||||
Field(SMBP, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset(0x40),
|
||||
, 2,
|
||||
I2CE, 1
|
||||
}
|
||||
|
||||
OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20)
|
||||
Field (SMBI, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
HSTS, 8, // Host Status
|
||||
, 8,
|
||||
HCNT, 8, // Host Control
|
||||
HCMD, 8, // Host Command
|
||||
TXSA, 8, // Transmit Slave Address
|
||||
DAT0, 8, // Host Data 0
|
||||
DAT1, 8, // Host Data 1
|
||||
HBDB, 8, // Host Block Data Byte
|
||||
PECK, 8, // Packet Error Check
|
||||
RXSA, 8, // Receive Slave Address
|
||||
RXDA, 16, // Receive Slave Data
|
||||
AUXS, 8, // Auxiliary Status
|
||||
AUXC, 8, // Auxiliary Control
|
||||
SLPC, 8, // SMLink Pin Control
|
||||
SBPC, 8, // SMBus Pin Control
|
||||
SSTS, 8, // Slave Status
|
||||
SCMD, 8, // Slave Command
|
||||
NADR, 8, // Notify Device Address
|
||||
NDLB, 8, // Notify Data Low Byte
|
||||
NDLH, 8, // Notify Data High Byte
|
||||
}
|
||||
|
||||
// Kill all SMBus communication
|
||||
Method (KILL, 0, Serialized)
|
||||
{
|
||||
Or (HCNT, 0x02, HCNT) // Send Kill
|
||||
Or (HSTS, 0xff, HSTS) // Clean Status
|
||||
}
|
||||
|
||||
// Check if last operation completed
|
||||
// return Failure = 0, Success = 1
|
||||
Method (CMPL, 0, Serialized)
|
||||
{
|
||||
Store (4000, Local0) // Timeout 200ms in 50us steps
|
||||
While (Local0) {
|
||||
If (And(HSTS, 0x02)) { // Completion Status?
|
||||
Return (1) // Operation Completed
|
||||
} Else {
|
||||
Stall (50)
|
||||
Decrement (Local0)
|
||||
If (LEqual(Local0, 0)) {
|
||||
KILL()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Return (0) // Failure
|
||||
}
|
||||
|
||||
|
||||
// Wait for SMBus to become ready
|
||||
Method (SRDY, 0, Serialized)
|
||||
{
|
||||
Store (200, Local0) // Timeout 200ms
|
||||
While (Local0) {
|
||||
If (And(HSTS, 0x40)) { // IN_USE?
|
||||
Sleep(1) // Wait 1ms
|
||||
Decrement(Local0) // timeout--
|
||||
If (LEqual(Local0, 0)) {
|
||||
Return (1)
|
||||
}
|
||||
} Else {
|
||||
Store (0, Local0) // We're ready
|
||||
}
|
||||
}
|
||||
|
||||
Store (4000, Local0) // Timeout 200ms (50us * 4000)
|
||||
While (Local0) {
|
||||
If (And (HSTS, 0x01)) { // Host Busy?
|
||||
Stall(50) // Wait 50us
|
||||
Decrement(Local0) // timeout--
|
||||
If (LEqual(Local0, 0)) {
|
||||
KILL()
|
||||
}
|
||||
} Else {
|
||||
Return (0) // Success
|
||||
}
|
||||
}
|
||||
|
||||
Return (1) // Failure
|
||||
}
|
||||
|
||||
// SMBus Send Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Data
|
||||
// Return: 1 = Success, 0=Failure
|
||||
|
||||
Method (SSXB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Send Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Arg0, TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Write Data
|
||||
|
||||
Store (0x48, HCNT) // Start + Byte Data Protocol
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (1) // Success
|
||||
}
|
||||
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Receive Byte
|
||||
// Arg0: Address
|
||||
// Return: 0xffff = Failure, Data (8bit) = Success
|
||||
|
||||
Method (SRXB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
// Receive Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Or (Arg0, 1), TXSA) // Write Address
|
||||
|
||||
Store (0x44, HCNT) // Start
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (DAT0) // Success
|
||||
}
|
||||
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Write Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Command
|
||||
// Arg2: Data
|
||||
// Return: 1 = Success, 0=Failure
|
||||
|
||||
Method (SWRB, 3, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Send Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Arg0, TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Write Command
|
||||
Store (Arg2, DAT0) // Write Data
|
||||
|
||||
Store (0x48, HCNT) // Start + Byte Protocol
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (1) // Success
|
||||
}
|
||||
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
// SMBus Read Byte
|
||||
// Arg0: Address
|
||||
// Arg1: Command
|
||||
// Return: 0xffff = Failure, Data (8bit) = Success
|
||||
|
||||
Method (SRDB, 2, Serialized)
|
||||
{
|
||||
|
||||
// Is the SMBus Controller Ready?
|
||||
If (SRDY()) {
|
||||
Return (0xffff)
|
||||
}
|
||||
|
||||
// Receive Byte
|
||||
Store (0, I2CE) // SMBus Enable
|
||||
Store (0xbf, HSTS)
|
||||
Store (Or (Arg0, 1), TXSA) // Write Address
|
||||
Store (Arg1, HCMD) // Command
|
||||
|
||||
Store (0x48, HCNT) // Start
|
||||
|
||||
If (CMPL()) {
|
||||
Or (HSTS, 0xff, HSTS) // Clean up
|
||||
Return (DAT0) // Success
|
||||
}
|
||||
|
||||
Return (0xffff)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
Loading…
Reference in New Issue