udelay: add missing bus frequency
commit 5b6404e419
("Fix timer frequency
detection on Sandybridge") reworked the udelay code, but didn't add
the 333MHz FSB entry used on Model 15 Xeons.
Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1099
Tested-by: build bot (Jenkins)
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@ -34,7 +34,7 @@ static int set_timer_fsb(void)
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{
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struct cpuinfo_x86 c;
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int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
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int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 };
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int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
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get_fms(&c, cpuid_eax(1));
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if (c.x86 != 6)
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@ -45,7 +45,7 @@ static int set_timer_fsb(void)
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case 0x1c: /* Atom */
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timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
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break;
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case 0xf: /* Core 2*/
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case 0xf: /* Core 2 or Xeon */
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case 0x17: /* Enhanced Core */
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timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
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break;
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