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udelay: add missing bus frequency 

commit 5b6404e419 ("Fix timer frequency
detection on Sandybridge") reworked the udelay code, but didn't add
the 333MHz FSB entry used on Model 15 Xeons.

Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1099
Tested-by: build bot (Jenkins)
This commit is contained in:
Sven Schnelle 2012-06-10 19:03:36 +02:00
parent bb1c42b920
commit 0860e723cb
1 changed files with 2 additions and 2 deletions
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4
src/cpu/x86/lapic/apic_timer.c
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@ -34,7 +34,7 @@ static int set_timer_fsb(void)
{ {
struct cpuinfo_x86 c; struct cpuinfo_x86 c;
int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 }; int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
get_fms(&c, cpuid_eax(1)); get_fms(&c, cpuid_eax(1));
if (c.x86 != 6) if (c.x86 != 6)
@ -45,7 +45,7 @@ static int set_timer_fsb(void)
case 0x1c: /* Atom */ case 0x1c: /* Atom */
timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
break; break;
case 0xf: /* Core 2*/ case 0xf: /* Core 2 or Xeon */
case 0x17: /* Enhanced Core */ case 0x17: /* Enhanced Core */
timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
break; break;