armv7: replace read/write macros with inlines
This enables type checking for safety as to help prevent errors like http://review.coreboot.org/#/c/3038/ . Now compilation fails if the wrong type is passed into readb/readw/readl/writeb/writew/writel or other macros in io.h. This also deprecates readw/writew. The previous definition was 16-bits which is incorrect since wordsize on ARMv7 is 32-bits and there was only 1 instance of writew (#if 0'd anyway). Going forward we should always use read{8,16,32} and write{8,16,32} where N specifies the exact length rather than relying on ambiguous definition of wordsize. Since many macros relied on __raw_*, which were basically the same (minus data memory barrier instructions), this patch also gets rid of __raw_*. There were parts of the code which ended up using these macros consecutively, for example: setbits_le32(®s->ch_cfg, SPI_CH_RST); clrbits_le32(®s->ch_cfg, SPI_CH_RST); In such cases the safe versions of readl() and writel() should be used anyway. Note: This also fixes two dubious casts as to avoid breaking compilation. Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3045 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks
Ronald G. Minnich
parent
b959fbb87a
commit
086b369dfc
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@ -1,6 +1,8 @@
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/*
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* linux/include/asm-arm/io.h
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* Originally imported from linux/include/asm-arm/io.h. This file has changed
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* substantially since then.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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@ -8,6 +10,7 @@
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 08-Apr-2013 G Replaced several macros with inlines for type safety.
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* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
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* constant addresses and variable addresses.
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* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
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@ -24,102 +27,53 @@
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#include <arch/cache.h> /* for dmb() */
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#include <arch/byteorder.h>
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static inline void sync(void)
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static inline uint8_t read8(const void *addr)
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{
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uint8_t v = *(volatile uint8_t *)addr;
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dmb();
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return v;
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}
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static inline uint16_t read16(const void *addr)
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{
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uint16_t v = *(volatile uint16_t *)addr;
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dmb();
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return v;
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}
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static inline uint32_t read32(const void *addr)
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{
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uint32_t v = *(volatile uint32_t *)addr;
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dmb();
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return v;
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}
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static inline void write8(uint8_t val, const void *addr)
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{
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dmb();
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*(volatile uint8_t *)addr = val;
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}
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static inline void write16(uint16_t val, const void *addr)
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{
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dmb();
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*(volatile uint16_t *)addr = val;
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}
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static inline void write32(uint32_t val, const void *addr)
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{
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dmb();
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*(volatile uint32_t *)addr = val;
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}
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/*
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* Generic virtual read/write. Note that we don't support half-word
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* read/writes. We define __arch_*[bl] here, and leave __arch_*w
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* to the architecture specific code.
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*/
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#define __arch_getb(a) (*(volatile unsigned char *)(a))
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#define __arch_getw(a) (*(volatile unsigned short *)(a))
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#define __arch_getl(a) (*(volatile unsigned int *)(a))
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#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
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#if 0
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extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
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{
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uint8_t *buf = (uint8_t *)data;
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while(bytelen--)
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__arch_putb(*buf++, addr);
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}
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extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
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{
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uint16_t *buf = (uint16_t *)data;
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while(wordlen--)
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__arch_putw(*buf++, addr);
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}
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extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
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{
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uint32_t *buf = (uint32_t *)data;
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while(longlen--)
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__arch_putl(*buf++, addr);
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}
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extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
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{
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uint8_t *buf = (uint8_t *)data;
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while(bytelen--)
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*buf++ = __arch_getb(addr);
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}
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extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
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{
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uint16_t *buf = (uint16_t *)data;
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while(wordlen--)
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*buf++ = __arch_getw(addr);
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}
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extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
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{
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uint32_t *buf = (uint32_t *)data;
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while(longlen--)
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*buf++ = __arch_getl(addr);
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}
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#endif
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#define __raw_writeb(v,a) __arch_putb(v,a)
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#define __raw_writew(v,a) __arch_putw(v,a)
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#define __raw_writel(v,a) __arch_putl(v,a)
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#define __raw_readb(a) __arch_getb(a)
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#define __raw_readw(a) __arch_getw(a)
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#define __raw_readl(a) __arch_getl(a)
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/*
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* TODO: The kernel offers some more advanced versions of barriers, it might
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* have some advantages to use them instead of the simple one here.
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*/
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#define __iormb() dmb()
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#define __iowmb() dmb()
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#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
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#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
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#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
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#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
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/*
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* The compiler seems to be incapable of optimising constants
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* properly. Spell it out to the compiler in some cases.
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* These are only valid for small values of "off" (< 1<<12)
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*/
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#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off)
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#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off)
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#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off)
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#define __raw_base_readb(base,off) __arch_base_getb(base,off)
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#define __raw_base_readw(base,off) __arch_base_getw(base,off)
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#define __raw_base_readl(base,off) __arch_base_getl(base,off)
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* FIXME: These are to avoid breaking existing ARM code. We should eventually
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* re-factor all code to specify the data length intended.
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*/
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#define readb(a) read8(a)
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#define writeb(v,a) write8(v,a)
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#define readl(a) read32(a)
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#define writel(v,a) write32(v,a)
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/*
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* Clear and set bits in one shot. These macros can be used to clear and
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@ -129,8 +83,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
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* in the 'set' parameter.
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*/
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#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
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#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
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#define out_arch(type,endian,a,v) write##type(cpu_to_##endian(v),a)
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#define in_arch(type,endian,a) endian##_to_cpu(read##type(a))
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#define out_le32(a,v) out_arch(l,le32,a,v)
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#define out_le16(a,v) out_arch(w,le16,a,v)
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@ -144,8 +98,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
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#define in_be32(a) in_arch(l,be32,a)
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#define in_be16(a) in_arch(w,be16,a)
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#define out_8(a,v) __raw_writeb(v,a)
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#define in_8(a) __raw_readb(a)
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#define out_8(a,v) writeb(v,a)
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#define in_8(a) readb(a)
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#define clrbits(type, addr, clear) \
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out_##type((addr), in_##type(addr) & ~(clear))
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@ -176,13 +130,6 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
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#define setbits_8(addr, set) setbits(8, addr, set)
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#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
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/*
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* Now, pick up the machine-defined IO definitions
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*/
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#if 0 /* XXX###XXX */
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#include <asm/arch/io.h>
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#endif /* XXX###XXX */
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/*
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* IO port access primitives
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* -------------------------
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@ -202,27 +149,26 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
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* address to a memory address.
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*
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* Note that we prevent GCC re-ordering or caching values in expressions
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* by introducing sequence points into the in*() definitions. Note that
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* __raw_* do not guarantee this behaviour.
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* by introducing sequence points into the in*() definitions.
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*
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* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
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*/
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#ifdef __io
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#define outb(v,p) __raw_writeb(v,__io(p))
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#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p))
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#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p))
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#define outb(v,p) writeb(v,__io(p))
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#define outw(v,p) writew(cpu_to_le16(v),__io(p))
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#define outl(v,p) writel(cpu_to_le32(v),__io(p))
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#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
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#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
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#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
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#define inb(p) ({ unsigned int __v = readb(__io(p)); __v; })
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#define inw(p) ({ unsigned int __v = le16_to_cpu(readw(__io(p))); __v; })
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#define inl(p) ({ unsigned int __v = le32_to_cpu(readl(__io(p))); __v; })
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#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
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#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
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#define outsb(p,d,l) writesb(__io(p),d,l)
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#define outsw(p,d,l) writesw(__io(p),d,l)
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#define outsl(p,d,l) writesl(__io(p),d,l)
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#define insb(p,d,l) __raw_readsb(__io(p),d,l)
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#define insw(p,d,l) __raw_readsw(__io(p),d,l)
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#define insl(p,d,l) __raw_readsl(__io(p),d,l)
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#define insb(p,d,l) readsb(__io(p),d,l)
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#define insw(p,d,l) readsw(__io(p),d,l)
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#define insl(p,d,l) readsl(__io(p),d,l)
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#endif
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#define outb_p(val,port) outb((val),(port))
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@ -285,13 +231,13 @@ extern void __readwrite_bug(const char *fn);
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*/
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#ifdef __mem_pci
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#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
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#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
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#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
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#define readb(c) ({ unsigned int __v = readb(__mem_pci(c)); __v; })
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#define readw(c) ({ unsigned int __v = le16_to_cpu(readw(__mem_pci(c))); __v; })
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#define readl(c) ({ unsigned int __v = le32_to_cpu(readl(__mem_pci(c))); __v; })
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#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
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#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
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#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
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#define writeb(v,c) writeb(v,__mem_pci(c))
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#define writew(v,c) writew(cpu_to_le16(v),__mem_pci(c))
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#define writel(v,c) writel(cpu_to_le32(v),__mem_pci(c))
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#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
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#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
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@ -316,66 +262,20 @@ check_signature(unsigned long io_addr, const unsigned char *signature,
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out:
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return retval;
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}
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#elif !defined(readb)
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#define readb(addr) (__readwrite_bug("readb"),0)
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#define readw(addr) (__readwrite_bug("readw"),0)
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#define readl(addr) (__readwrite_bug("readl"),0)
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#define writeb(v,addr) __readwrite_bug("writeb")
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#define writew(v,addr) __readwrite_bug("writew")
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#define writel(v,addr) __readwrite_bug("writel")
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#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum")
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#define check_signature(io,sig,len) (0)
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#endif /* __mem_pci */
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/* FIXME(dhendrix): added to make uart8250_mem code happy. Note: lL */
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static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
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{
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return readb(addr);
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}
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static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
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{
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return readw(addr);
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}
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static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
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{
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return readl(addr);
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}
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static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
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{
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writeb(value, addr);
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}
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static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
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{
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writew(value, addr);
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}
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static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
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{
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writel(value, addr);
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}
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/*
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* If this architecture has ISA IO, then define the isa_read/isa_write
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* macros.
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*/
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#ifdef __mem_isa
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#define isa_readb(addr) __raw_readb(__mem_isa(addr))
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#define isa_readw(addr) __raw_readw(__mem_isa(addr))
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#define isa_readl(addr) __raw_readl(__mem_isa(addr))
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#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr))
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#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr))
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#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr))
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#define isa_readb(addr) readb(__mem_isa(addr))
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#define isa_readw(addr) readw(__mem_isa(addr))
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#define isa_readl(addr) readl(__mem_isa(addr))
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#define isa_writeb(val,addr) writeb(val,__mem_isa(addr))
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#define isa_writew(val,addr) writew(val,__mem_isa(addr))
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#define isa_writel(val,addr) writel(val,__mem_isa(addr))
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#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c))
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#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c))
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#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c))
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@ -65,7 +65,7 @@ int s5p_get_cpu_rev(void)
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void s5p_set_cpu_id(void)
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{
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s5p_cpu_id = readl(EXYNOS_PRO_ID);
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s5p_cpu_id = readl((void *)EXYNOS_PRO_ID);
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s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
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/*
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@ -379,7 +379,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
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{
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struct exynos5_clock *clk =
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samsung_get_base_clock();
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unsigned int addr;
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unsigned int *addr;
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unsigned int val;
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/*
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@ -389,9 +389,9 @@ void set_mmc_clk(int dev_index, unsigned int div)
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* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
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*/
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if (dev_index < 2) {
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addr = (unsigned int)&clk->div_fsys1;
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addr = &clk->div_fsys1;
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} else {
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addr = (unsigned int)&clk->div_fsys2;
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addr = &clk->div_fsys2;
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dev_index -= 2;
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}
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@ -106,7 +106,7 @@ static void serial_setbrg_dev(void)
|
|||
*/
|
||||
#if 0
|
||||
if (s5p_uart_divslot())
|
||||
writew(udivslot[val % 16], &uart->rest.slot);
|
||||
writel(udivslot[val % 16], &uart->rest.slot);
|
||||
else
|
||||
writeb(val % 16, &uart->rest.value);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue