soc/intel/tigerlake: Correct GPIO community PID configuration

Current implementation returns the incorrect GPIO community PID.
The GPIO community index 3 should return PID for COMM_4 and index
4 should return PID for COMM_5.

TEST=Verify PCR port id is correct for each community.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5dc48e5b31f43853b3a613c17f13f7df71f1fbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41725
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2020-05-26 20:10:22 +08:00 committed by Patrick Georgi
parent be7507db29
commit 087064f471
1 changed files with 5 additions and 5 deletions

View File

@ -106,19 +106,19 @@ Method (GPID, 1, Serialized)
{ {
Switch (ToInteger (Arg0)) Switch (ToInteger (Arg0))
{ {
Case (0) { Case (COMM_0) {
Local0 = PID_GPIOCOM0 Local0 = PID_GPIOCOM0
} }
Case (1) { Case (COMM_1) {
Local0 = PID_GPIOCOM1 Local0 = PID_GPIOCOM1
} }
Case (2) { Case (COMM_2) {
Local0 = PID_GPIOCOM2 Local0 = PID_GPIOCOM2
} }
Case (4) { Case (COMM_4) {
Local0 = PID_GPIOCOM4 Local0 = PID_GPIOCOM4
} }
Case (5) { Case (COMM_5) {
Local0 = PID_GPIOCOM5 Local0 = PID_GPIOCOM5
} }
Default { Default {