arch/x86: Drop leftover ROMCC support
Remove the last bits of building romstage with romcc. Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -107,10 +107,6 @@ config NUM_IPI_STARTS
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int
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default 2
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config ROMCC
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bool
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default n
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config CBMEM_TOP_BACKUP
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def_bool n
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help
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@ -223,46 +223,7 @@ romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
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romstage-y += postcar_loader.c
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romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
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ifneq ($(CONFIG_ROMCC),y)
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romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
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else # CONFIG_ROMCC == y
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# This order matters. The mainboards requiring ROMCC need their mainboard
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# code to follow the prior crt0s files for program flow control. The
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# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage
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# because of the instruction sequen fall-through.
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crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
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crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc
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ifeq ($(CONFIG_MMX),y)
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ifeq ($(CONFIG_SSE),y)
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ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE
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else
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ROMCCFLAGS := -mcpu=p2 -O2 # MMX, !SSE
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endif
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else
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ROMCCFLAGS := -mcpu=i386 -O2 # !MMX, !SSE
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endif
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$(objcbfs)/romstage%.bin: $(objcbfs)/romstage%.elf
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@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
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$(OBJCOPY_romstage) -O binary $< $@
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$(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug
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@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
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cp $< $@.tmp
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$(OBJCOPY_romstage) --strip-debug $@.tmp
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$(OBJCOPY_romstage) --add-gnu-debuglink=$< $@.tmp
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mv $@.tmp $@
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$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
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printf " ROMCC romstage.inc\n"
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$(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@
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endif
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romstage-libs ?=
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$(eval $(call early_x86_assembly_entry_rule,romstage))
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@ -1,26 +0,0 @@
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/*
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* Copyright 2002 Eric Biederman
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*
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* This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/post_code.h>
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* clear direction flag */
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movl $CONFIG_RAMTOP, %esp
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movl %esp, %ebp
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call copy_and_run
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.Lhlt:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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@ -8,7 +8,7 @@ if ARCH_X86
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config CACHE_AS_RAM
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bool
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default !ROMCC
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default y
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config NO_CAR_GLOBAL_MIGRATION
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bool
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@ -35,8 +35,5 @@ static void StartTimer1(void)
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void SystemPreInit(void)
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{
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/* they want a jump ... */
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#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
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__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
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#endif
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StartTimer1();
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}
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@ -88,7 +88,6 @@ config NO_FIXED_XIP_ROM_SIZE
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config XIP_ROM_SIZE
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hex
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depends on !NO_FIXED_XIP_ROM_SIZE
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default ROM_SIZE if ROMCC
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default 0x10000
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config CPU_ADDR_BITS
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