mb/system76/gaze15: Convert to variant setup

Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/system76/gaze15/Kconfig

@@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_TPM2
 	select NO_UART_ON_SUPERIO
 	select SOC_INTEL_CANNONLAKE_PCH_H
-	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COMETLAKE_1 if BOARD_SYSTEM76_GAZE15
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
@@ -25,45 +25,43 @@ config BOARD_SPECIFIC_OPTIONS
 config MAINBOARD_DIR
 	default "system76/gaze15"
 
+config VARIANT_DIR
+	default "gaze15" if BOARD_SYSTEM76_GAZE15
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
 config MAINBOARD_PART_NUMBER
-	default "gaze15"
+	default "gaze15" if BOARD_SYSTEM76_GAZE15
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
-	string
 	default "Gazelle"
 
 config MAINBOARD_VERSION
-	string
-	default "gaze15"
+	default "gaze15" if BOARD_SYSTEM76_GAZE15
 
 config CBFS_SIZE
 	default 0xA00000
 
 config CONSOLE_POST
-	bool
 	default y
 
 config ONBOARD_VGA_IS_PRIMARY
-	bool
 	default y
 
 config UART_FOR_CONSOLE
-	int
 	default 2
 
 config MAX_CPUS
-	int
 	default 16
 
 config DIMM_MAX
 	default 2
 
 config VGA_BIOS_ID
-	string
 	default "8086,9bc4"
 
 config POST_DEVICE
-	bool
 	default n
 
 endif

src/mainboard/system76/gaze15/Makefile.inc

@@ -1,8 +1,10 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 bootblock-y += bootblock.c
-bootblock-y += gpio_early.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += romstage.c
 
 ramstage-y += ramstage.c
-ramstage-y += gpio.c
-ramstage-y += hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/gaze15/board_info.txt

@@ -1,7 +1,5 @@
 Vendor name: System76
-Board name: gaze15
 Category: laptop
-Release year: 2020
 ROM package: SOIC-8
 ROM protocol: SPI
 ROM socketed: n

src/mainboard/system76/gaze15/bootblock.c

@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
-#include <gpio.h>
-#include <mainboard/gpio.h>
+#include <variant/gpio.h>
 
 void bootblock_mainboard_early_init(void)
 {
-	mainboard_configure_early_gpios();
+	variant_configure_early_gpios();
 }

src/mainboard/system76/gaze15/devicetree.cb

@@ -22,14 +22,6 @@ chip soc/intel/cannonlake
 	register "enable_c6dram" = "1"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
-	# Serial I/O
-	register "SerialIoDevMode" = "{
-		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
-		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
-		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
-	}"
-
-
 	# Misc
 	register "AcousticNoiseMitigation" = "1"
 
@@ -60,7 +52,6 @@ chip soc/intel/cannonlake
 	end
 
 	device domain 0 on
-		subsystemid 0x1558 0x8520 inherit
 		device pci 00.0 on  end # Host Bridge
 		device pci 01.0 on      # GPU Port
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
@@ -101,24 +92,6 @@ chip soc/intel/cannonlake
 			end
 		end
 		device pci 14.5 off end # SDCard
-		device pci 15.0 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
-				register "generic.probed" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
-				register "generic.desc" = ""Synaptics Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
-				register "generic.probed" = "1"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
-			end
-		end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
@@ -192,7 +165,7 @@ chip soc/intel/cannonlake
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on # LPC Interface
+		device pci 1f.0 on      # LPC Interface
 			register "gen1_dec" = "0x00040069"
 			register "gen2_dec" = "0x00fc0e01"
 			register "gen3_dec" = "0x00fc0f01"

src/mainboard/system76/gaze15/dsdt.asl

@@ -7,7 +7,7 @@ DefinitionBlock(
 	ACPI_DSDT_REV_2,
 	OEM_ID,
 	ACPI_TABLE_CREATOR,
-	0x20110725	/* OEM revision */
+	0x20110725
 )
 {
 	#include <acpi/dsdt_top.asl>

src/mainboard/system76/gaze15/include/mainboard/gpio.h

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
-
-void mainboard_configure_early_gpios(void);
-void mainboard_configure_gpios(void);
-
-#endif

src/mainboard/system76/gaze15/include/variant/gpio.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+
+#endif

src/mainboard/system76/gaze15/ramstage.c

@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mainboard/gpio.h>
 #include <device/device.h>
+#include <variant/gpio.h>
 
-static void init_mainboard(void *chip_info)
+static void mainboard_init(void *chip_info)
 {
-	mainboard_configure_gpios();
+	variant_configure_gpios();
 }
 
 struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
+	.init = mainboard_init,
 };

src/mainboard/system76/gaze15/variants/gaze15/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze15
+Release year: 2020

src/mainboard/system76/gaze15/variants/gaze15/gpio.c

@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mainboard/gpio.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
+#include <variant/gpio.h>
 
 static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPD ------- */
@@ -271,7 +271,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT#
 };
 
-void mainboard_configure_gpios(void)
+void variant_configure_gpios(void)
 {
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }

src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mainboard/gpio.h>
 #include <soc/gpio.h>
+#include <variant/gpio.h>
 
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
@@ -11,7 +11,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
 };
 
-void mainboard_configure_early_gpios(void)
+void variant_configure_early_gpios(void)
 {
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }

src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb

@@ -0,0 +1,31 @@
+chip soc/intel/cannonlake
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
+	}"
+
+	device domain 0 on
+		subsystemid 0x1558 0x8520 inherit
+
+		device pci 15.0 on      # I2C0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+	end
+end