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northbridge/intel: Do not define include guard as 1 

As `#ifndef` and not `#if` is used in the check for
include guards, setting it to 1 is not needed.

Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8103
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Edward O'Callaghan 2015-01-06 02:48:57 +11:00
parent ebe3a7aea3
commit 089a510292
9 changed files with 17 additions and 17 deletions
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2
src/northbridge/intel/fsp_rangeley/northbridge.h
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@ -20,7 +20,7 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1 #define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS

4
src/northbridge/intel/fsp_sandybridge/northbridge.h
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@ -20,7 +20,7 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
/* Chipset types */ /* Chipset types */
#define SANDYBRIDGE_MOBILE 0 #define SANDYBRIDGE_MOBILE 0
@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif
#endif #endif
#endif #endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */

4
src/northbridge/intel/gm45/delay.h
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@ -18,11 +18,11 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__ #ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__
#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ 1 #define __NORTHBRIDGE_INTEL_GM45_DELAY_H__
#include <delay.h> #include <delay.h>
void ns100delay(u32); void ns100delay(u32);
void udelay_from_reset(u32); void udelay_from_reset(u32);
#endif #endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */

4
src/northbridge/intel/gm45/gm45.h
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@ -19,7 +19,7 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__
#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ 1 #define __NORTHBRIDGE_INTEL_GM45_GM45_H__
#include "southbridge/intel/i82801ix/i82801ix.h" #include "southbridge/intel/i82801ix/i82801ix.h"
@ -434,4 +434,4 @@ struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp);
#endif #endif
#endif #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */

4
src/northbridge/intel/haswell/haswell.h
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@ -19,7 +19,7 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ 1 #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
/* Chipset types */ /* Chipset types */
#define HASWELL_MOBILE 0 #define HASWELL_MOBILE 0
@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif
#endif #endif
#endif #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */

4
src/northbridge/intel/nehalem/gma.h
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@ -19,7 +19,7 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ #ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__
#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ 1 #define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__
/* mailbox 0: header */ /* mailbox 0: header */
typedef struct { typedef struct {
@ -118,4 +118,4 @@ typedef struct {
opregion_vbt_t vbt; opregion_vbt_t vbt;
} __attribute__((packed)) igd_opregion_t; } __attribute__((packed)) igd_opregion_t;
#endif #endif /* __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ */

4
src/northbridge/intel/nehalem/nehalem.h
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@ -20,7 +20,7 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ #ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ 1 #define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
@ -623,4 +623,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif
#endif #endif
#endif #endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */

4
src/northbridge/intel/sandybridge/sandybridge.h
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@ -19,7 +19,7 @@
*/ */
#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
/* Chipset types */ /* Chipset types */
#define SANDYBRIDGE_MOBILE 0 #define SANDYBRIDGE_MOBILE 0
@ -240,4 +240,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif #endif
#endif #endif
#endif #endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */

4
src/northbridge/intel/sch/sch.h
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@ -20,7 +20,7 @@
*/ */
#ifndef __SCH_PULSBO_H__ #ifndef __SCH_PULSBO_H__
#define __SCH_PULSBO_H__ 1 #define __SCH_PULSBO_H__
int sch_port_access_read(int port, int reg, int bytes); int sch_port_access_read(int port, int reg, int bytes);
void sch_port_access_write(int port, int reg, int bytes, long data); void sch_port_access_write(int port, int reg, int bytes, long data);
@ -51,4 +51,4 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
/* FIXME: should probably be in southbridge, but is setup in romstage, too */ /* FIXME: should probably be in southbridge, but is setup in romstage, too */
#define CMC_SHADOW 0x3faf0000 #define CMC_SHADOW 0x3faf0000
#endif #endif /* __SCH_PULSBO_H__ */