google/grunt: Override BayHub EMMC driving strength
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure. It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for this issue. CLK[6:4] CMD,DATA[3:1] original register value: 0x6B enhanced: 0x7F BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27816 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -21,28 +21,11 @@
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#include <device/pci.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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#include "chip.h"
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#include "bh720.h"
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enum {
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__attribute__((weak)) void bh720_driving_strength(struct device *dev)
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BH720_PROTECT = 0xd0,
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{
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BH720_PROTECT_LOCK_OFF = 0,
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}
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BH720_PROTECT_LOCK_ON = BIT(0),
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BH720_PROTECT_OFF = 0,
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BH720_PROTECT_ON = BIT(31),
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BH720_LINK_CTRL = 0x90,
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BH720_LINK_CTRL_L0_ENABLE = BIT(0),
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BH720_LINK_CTRL_L1_ENABLE = BIT(1),
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BH720_LINK_CTRL_CLKREQ = BIT(8),
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BH720_MISC2 = 0xf0,
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BH720_MISC2_ASPM_DISABLE = BIT(0),
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BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
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BH720_MISC2_APSM_PHY_L1 = BIT(10),
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BH720_MISC2_APSM_MORE = BIT(12),
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BH720_RTD3_L1 = 0x3e0,
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BH720_RTD3_L1_DISABLE_L1 = BIT(28),
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};
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static void bh720_init(struct device *dev)
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static void bh720_init(struct device *dev)
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{
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{
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@ -71,6 +54,8 @@ static void bh720_init(struct device *dev)
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printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
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printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
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pci_read_config32(dev, BH720_LINK_CTRL));
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pci_read_config32(dev, BH720_LINK_CTRL));
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}
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}
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bh720_driving_strength(dev);
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}
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}
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static struct pci_operations pci_ops = {
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static struct pci_operations pci_ops = {
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@ -0,0 +1,47 @@
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/*
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* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge
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*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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enum {
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BH720_PROTECT = 0xd0,
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BH720_PROTECT_LOCK_OFF = 0,
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BH720_PROTECT_LOCK_ON = BIT(0),
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BH720_PROTECT_OFF = 0,
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BH720_PROTECT_ON = BIT(31),
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BH720_LINK_CTRL = 0x90,
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BH720_LINK_CTRL_L0_ENABLE = BIT(0),
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BH720_LINK_CTRL_L1_ENABLE = BIT(1),
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BH720_LINK_CTRL_CLKREQ = BIT(8),
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BH720_MISC2 = 0xf0,
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BH720_MISC2_ASPM_DISABLE = BIT(0),
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BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
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BH720_MISC2_APSM_PHY_L1 = BIT(10),
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BH720_MISC2_APSM_MORE = BIT(12),
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BH720_MEM_RW_DATA = 0x200,
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BH720_MEM_RW_ADR = 0x204,
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BH720_MEM_ACCESS_EN = 0x208,
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BH720_PCR = 0x304,
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BH720_PCR_DATA_CMD_DRV_MAX = 7,
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BH720_PCR_CLK_DRV_MAX = 7,
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BH720_RTD3_L1 = 0x3e0,
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BH720_RTD3_L1_DISABLE_L1 = BIT(28),
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};
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void bh720_driving_strength(struct device *dev);
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@ -17,7 +17,8 @@
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <gpio.h>
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#include <variant/gpio.h>
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#include <variant/gpio.h>
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#include <device/pci.h>
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#include <drivers/generic/bayhub/bh720.h>
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uint8_t variant_board_sku(void)
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uint8_t variant_board_sku(void)
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{
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{
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@ -36,3 +37,26 @@ void variant_mainboard_suspend_resume(void)
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gpio_set(GPIO_133, 0);
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gpio_set(GPIO_133, 0);
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}
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}
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#endif
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#endif
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void bh720_driving_strength(struct device *dev)
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{
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u32 sdbar;
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u32 bh720_pcr_data;
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sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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/* Enable Memory Access Function */
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write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
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write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000);
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write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
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/* Read current EMMC 1.8V CLK/DATA,CMD driving strength */
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write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x40000304);
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bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
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/* set EMMC 1.8V CLK/DATA,CMD the max level */
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write32((void *)(sdbar + BH720_MEM_RW_DATA),
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bh720_pcr_data | (BH720_PCR_CLK_DRV_MAX << 4) |
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(BH720_PCR_DATA_CMD_DRV_MAX << 1));
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write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x80000304);
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}
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