intel/fsp_baytrail: Enable LPSS in ACPI mode
This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would result in unusable devices, as the resources were set to 0 and the devices were disabled. lpss.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode set to disable and the devicetree set to default. Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Ben Gardner
Martin Roth
parent
59be62480e
commit
08bfba4f02
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@ -50,6 +50,7 @@ ramstage-y += reset.c
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ramstage-y += cpu.c
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ramstage-y += acpi.c
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ramstage-y += lpe.c
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ramstage-y += lpss.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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@ -0,0 +1,202 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <soc/iosf.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
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{
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struct reg_script ops[] = {
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/* Disable PCI interrupt, enable Memory and Bus Master */
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REG_PCI_OR32(PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
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/* Enable ACPI mode */
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REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
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LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
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REG_SCRIPT_END
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};
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struct resource *bar;
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global_nvs_t *gnvs;
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/* Find ACPI NVS to update BARs */
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gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (!gnvs) {
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printk(BIOS_ERR, "Unable to locate Global NVS\n");
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return;
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}
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/* Save BAR0 and BAR1 to ACPI NVS */
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bar = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (bar)
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gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base;
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bar = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (bar)
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gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base;
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/* Device is enabled in ACPI mode */
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gnvs->dev.lpss_en[nvs_index] = 1;
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/* Put device in ACPI mode */
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reg_script_run_on_dev(dev, ops);
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}
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static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
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{
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struct reg_script ops[] = {
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REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
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~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP),
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LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT),
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REG_SCRIPT_END,
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};
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reg_script_run_on_dev(dev, ops);
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}
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static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
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{
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*iosf_reg = -1;
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*nvs_index = -1;
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#define SET_IOSF_REG(name_) \
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case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
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*iosf_reg = LPSS_ ## name_ ## _CTL; \
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*nvs_index = LPSS_NVS_ ## name_
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switch (dev->path.pci.devfn) {
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SET_IOSF_REG(SIO_DMA1);
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break;
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SET_IOSF_REG(I2C1);
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break;
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SET_IOSF_REG(I2C2);
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break;
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SET_IOSF_REG(I2C3);
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break;
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SET_IOSF_REG(I2C4);
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break;
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SET_IOSF_REG(I2C5);
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break;
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SET_IOSF_REG(I2C6);
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break;
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SET_IOSF_REG(I2C7);
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break;
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SET_IOSF_REG(SIO_DMA2);
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break;
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SET_IOSF_REG(PWM1);
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break;
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SET_IOSF_REG(PWM2);
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break;
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SET_IOSF_REG(HSUART1);
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break;
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SET_IOSF_REG(HSUART2);
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break;
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SET_IOSF_REG(SPI);
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break;
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}
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}
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static void i2c_disable_resets(device_t dev)
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{
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/* Release the I2C devices from reset. */
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static const struct reg_script ops[] = {
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3),
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REG_SCRIPT_END,
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};
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#define CASE_I2C(name_) \
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case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
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switch (dev->path.pci.devfn) {
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CASE_I2C(I2C1):
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CASE_I2C(I2C2):
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CASE_I2C(I2C3):
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CASE_I2C(I2C4):
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CASE_I2C(I2C5):
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CASE_I2C(I2C6):
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CASE_I2C(I2C7):
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printk(BIOS_DEBUG, "Releasing I2C device from reset.\n");
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reg_script_run_on_dev(dev, ops);
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break;
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default:
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return;
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}
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}
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static void lpss_init(device_t dev)
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{
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struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
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int iosf_reg, nvs_index;
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dev_ctl_reg(dev, &iosf_reg, &nvs_index);
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if (iosf_reg < 0) {
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int slot = PCI_SLOT(dev->path.pci.devfn);
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int func = PCI_FUNC(dev->path.pci.devfn);
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printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n",
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slot, func);
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return;
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}
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dev_enable_snoop_and_pm(dev, iosf_reg);
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i2c_disable_resets(dev);
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if (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE)
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dev_enable_acpi_mode(dev, iosf_reg, nvs_index);
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}
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static struct device_operations device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = lpss_init,
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.enable = NULL,
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.scan_bus = NULL,
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.ops_pci = &soc_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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SIO_DMA1_DEVID,
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I2C1_DEVID,
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I2C2_DEVID,
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I2C3_DEVID,
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I2C4_DEVID,
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I2C5_DEVID,
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I2C6_DEVID,
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I2C7_DEVID,
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SIO_DMA2_DEVID,
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PWM1_DEVID,
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PWM2_DEVID,
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HSUART1_DEVID,
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HSUART2_DEVID,
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SPI_DEVID,
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0,
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};
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static const struct pci_driver southcluster __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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