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AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. 

Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Kerry She 2010-09-04 06:13:02 +00:00 committed by Patrick Georgi
parent c914053026
commit 08c92e03bf
2 changed files with 4 additions and 2 deletions
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3
src/northbridge/amd/amdmct/mct/mct_d.c
View File

@ -3461,9 +3461,10 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
i = 0; /* use i for the dct setting required */
if (pDCTstat->MAdimms[0] < 4)
i = 1;
if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4))
if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) {
dword &= 0xF18FFF18;
index_reg = 0x98; /* force dct = 0 */
}
}
Set_NB32_index_wait(dev, index_reg, 0x0a, dword);

3
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -3127,9 +3127,10 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
i = 0; /* use i for the dct setting required */
if (pDCTstat->MAdimms[0] < 4)
i = 1;
if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4))
if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) {
dword &= 0xF18FFF18;
index_reg = 0x98; /* force dct = 0 */
}
}
Set_NB32_index_wait(dev, index_reg, 0x0a, dword);