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soc/mediatek/mt8186: Lower SPI NOR speed to 52MHiz 

The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's
HW design, which is capable of up to 52MHz. Therefore, lower the speed
to univpll_d3_d8 (52MHz).

BUG=b:218775654
TEST=emerge-corsola coreboot
TEST=Boot time didn't increase significantly
BRAHCH=none

Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Yu-Ping Wu 2022-02-10 17:00:17 +08:00 committed by Felix Held
parent e527c713bd
commit 08d2016e50
1 changed files with 1 additions and 1 deletions
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src/soc/mediatek/mt8186/pll.c
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@ -253,7 +253,7 @@ static const struct mux_sel mux_sels[] = {
{ .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d3_d2 */
{ .id = TOP_SPMI_MST_SEL, .sel = 2 }, /* 2: ulposc1_d4 */
/* CLK_CFG_13 */
{ .id = TOP_SPINOR_SEL, .sel = 5 }, /* 5: mainpll_d7_d2 */
{ .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d3_d8 */
{ .id = TOP_NNA_SEL, .sel = 14 }, /* 14: nnapll_ck */
{ .id = TOP_NNA1_SEL, .sel = 14 }, /* 14: nnapll_ck */
{ .id = TOP_NNA2_SEL, .sel = 15 }, /* 15: nna2pll_ck */